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Improved CPU identification and initialization routines. This

Browse source 
supports All Cyrix CPUs, IBM Blue Lightning CPU and NexGen (now AMD)
Nx586 CPU, and initialize special registers of Cyrix CPU and msr of
IBM Blue Lightning CPU.

If revision of Cyrix 6x86 CPU < 2.7, CPU cache is enabled in
write-through mode.  This can be disabled by kernel configuration
options.

Reviewed by:	Bruce Evans <bde@freebsd.org> and
            	Jordan K. Hubbard <jkh@freebsd.org>
This commit is contained in:
KATO Takenori 1997-03-22 18:54:54 +00:00
parent 0b6f152321
commit 4c024bbdf8
32 changed files with 1413 additions and 1503 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

297
sys/amd64/amd64/identcpu.c
View file

@ -1,6 +1,7 @@
/*-
/*
* Copyright (c) 1992 Terrence R. Lambert.
* Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
* Copyright (c) 1997 KATO Takenori.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
@ -35,7 +36,7 @@
* SUCH DAMAGE.
*
* from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
* $Id$
* $Id: identcpu.c,v 1.13 1997/02/22 09:32:19 peter Exp $
*/
#include "opt_cpu.h"
@ -54,12 +55,18 @@
#include <machine/sysarch.h>
#include <machine/md_var.h>
#include <i386/isa/isa_device.h>
/* XXX - should be in header file */
void i486_bzero __P((void *buf, size_t len));
void identifycpu(void); /* XXX should be in different header file */
void printcpuinfo(void); /* XXX should be in different header file */
void finishidentcpu(void);
void earlysetcpuclass(void);
void panicifcpuunsupported(void);
static void identifycyrix(void);
u_long cyrix_did; /* Device ID of Cyirx CPU */
int cpu_class = CPUCLASS_386; /* least common denominator */
char machine[] = "i386";
SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
@ -74,13 +81,19 @@ static struct cpu_nameclass i386_cpus[] = {
{ "i486SX", CPUCLASS_486 }, /* CPU_486SX */
{ "i486DX", CPUCLASS_486 }, /* CPU_486 */
{ "Pentium", CPUCLASS_586 }, /* CPU_586 */
{ "Cy486DLC", CPUCLASS_486 }, /* CPU_486DLC */
{ "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
{ "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
{ "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
{ "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
{ "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
{ "Cyrix 6x86 MMX", CPUCLASS_586 }, /* CPU_M2 (XXX) */
{ "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
};
void
identifycpu(void)
printcpuinfo(void)
{
cpu_class = i386_cpus[cpu].cpu_class;
printf("CPU: ");
strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof cpu_model);
@ -140,7 +153,6 @@ identifycpu(void)
* Values taken from AMD Processor Recognition
* http://www.amd.com/html/products/pcd/techdocs/appnotes/20734c.pdf
*/
cpu_model[0] = '\0';
strcpy(cpu_model, "AMD ");
switch (cpu_id & 0xFF0) {
case 0x4E0:
@ -162,8 +174,119 @@ identifycpu(void)
strcat(cpu_model, "Unknown");
break;
}
}
} else if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
strcpy(cpu_model, "Cyrix ");
switch (cyrix_did & 0xf0) {
case 0x00:
switch (cyrix_did & 0x0f) {
case 0x00:
strcat(cpu_model, "486SLC");
break;
case 0x01:
strcat(cpu_model, "486DLC");
break;
case 0x02:
strcat(cpu_model, "486SLC2");
break;
case 0x03:
strcat(cpu_model, "486DLC2");
break;
case 0x04:
strcat(cpu_model, "486SRx");
break;
case 0x05:
strcat(cpu_model, "486DRx");
break;
case 0x06:
strcat(cpu_model, "486SRx2");
break;
case 0x07:
strcat(cpu_model, "486DRx2");
break;
case 0x08:
strcat(cpu_model, "486SRu");
break;
case 0x09:
strcat(cpu_model, "486DRu");
break;
case 0x0a:
strcat(cpu_model, "486SRu2");
break;
case 0x0b:
strcat(cpu_model, "486DRu2");
break;
default:
strcat(cpu_model, "Unknown");
break;
}
break;
case 0x10:
switch (cyrix_did & 0x0f) {
case 0x00:
strcat(cpu_model, "486S");
break;
case 0x01:
strcat(cpu_model, "486S2");
break;
case 0x02:
strcat(cpu_model, "486Se");
break;
case 0x03:
strcat(cpu_model, "486S2e");
break;
case 0x0a:
strcat(cpu_model, "486DX");
break;
case 0x0b:
strcat(cpu_model, "486DX2");
break;
case 0x0f:
strcat(cpu_model, "486DX4");
break;
default:
strcat(cpu_model, "Unknown");
break;
}
break;
case 0x20:
if ((cyrix_did & 0x0f) < 8)
strcat(cpu_model, "6x86"); /* Where did you get it? */
else
strcat(cpu_model, "5x86");
break;
case 0x30:
strcat(cpu_model, "6x86");
break;
case 0x40:
/* XXX */
strcat(cpu_model, "Gx86");
break;
case 0x50:
strcat(cpu_model, "Enhanced 6x86 with MMX");
break;
case 0xf0:
switch (cyrix_did & 0x0f) {
case 0x0d:
strcat(cpu_model, "Overdrive CPU");
case 0x0e:
strcpy(cpu_model, "Texas Instruments 486SXL");
break;
case 0x0f:
strcat(cpu_model, "486SLC/DLC");
break;
default:
strcat(cpu_model, "Unknown");
break;
}
break;
default:
strcat(cpu_model, "Unknown");
break;
}
} else if (strcmp(cpu_vendor,"IBM") == 0)
strcpy(cpu_model, "Blue Lightning CPU");
#endif
printf("%s (", cpu_model);
switch(cpu_class) {
case CPUCLASS_286:
@ -238,6 +361,14 @@ identifycpu(void)
"\020CMOV"
);
}
} else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
printf(" Device ID = 0x%lx", cyrix_did);
printf(" Stepping=%ld", (cyrix_did & 0xf000) >> 12);
printf(" Revision=%ld", (cyrix_did & 0x0fff) >> 8);
#ifndef CYRIX_CACHE_REALLY_WORKS
if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
printf("\n CPU cache: write-through mode");
#endif
}
/* Avoid ugly blank lines: only print newline when we have to. */
if (*cpu_vendor || cpu_id)
@ -248,6 +379,11 @@ identifycpu(void)
* XXX - Do PPro CPUID level=2 stuff here?
*/
#endif
}
void
panicifcpuunsupported(void)
{
/*
* Now that we have told the user what they have,
@ -276,6 +412,152 @@ identifycpu(void)
}
}
static volatile u_int trap_by_wrmsr;
/*
* Special exception 16 handler.
* The wrmsr instruction generates invalid opcodes fault on 486-class
* Cyrix CPU. Stacked eip register points the wrmsr instruction in the
* function identblue() when this handler is called. Stacked eip should
* be advanced.
*/
inthand_t bluetrap;
asm
("
.text
_bluetrap:
ss
movl $0xa8c1d, _trap_by_wrmsr # Don't ask meaning of the number :-).
addl $2, (%esp) # I know wrmsr is a 2-bytes instruction.
iret
");
/*
* Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
* support cpuid instruction. This function should be called after
* loading interrupt descriptor table register.
*
* I don't like this method that handles fault, but I couldn't get
* information for any other methods. Does blue giant know?
*/
static int
identblue(void)
{
trap_by_wrmsr = 0;
/*
* Cyrix 486-class CPU does not support wrmsr instruction.
* The wrmsr instruction causes invalid opcode fault, and exception
* will be trapped by bluetrap() on Cyrix 486-class CPU. The bluetrap()
* set the magic number to tra_by_wrmsr.
*/
setidt(6, bluetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
wrmsr(0x1002, 0x03000000LL); /* Fault on Cyrix 486-class CPU. */
if (trap_by_wrmsr == 0xa8c1d)
return 0; /* Cyrix CPU sets the magic number. */
return 1; /* IBM Blue Lightnig CPU */
}
/*
* identifycyrix() set lower 16 bits of cyrix_did as follows:
*
* F E D C B A 9 8 7 6 5 4 3 2 1 0
* +-------+-------+---------------+
* | SID | RID | Device ID |
* | (DIR 1) | (DIR 0) |
* +-------+-------+---------------+
*/
static void
identifycyrix(void)
{
u_long eflags;
int ccr2_test = 0, dir_test = 0;
u_char ccr2, ccr3;
eflags = read_eflags();
disable_intr();
ccr2 = read_cyrix_reg(CCR2);
write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
read_cyrix_reg(CCR2);
if (read_cyrix_reg(CCR2) != ccr2)
ccr2_test = 1;
write_cyrix_reg(CCR2, ccr2);
ccr3 = read_cyrix_reg(CCR3);
write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
read_cyrix_reg(CCR3);
if (read_cyrix_reg(CCR3) != ccr3)
dir_test = 1; /* CPU supports DIRs. */
write_cyrix_reg(CCR3, ccr3);
if (dir_test) {
/* Device ID registers are available. */
cyrix_did = read_cyrix_reg(DIR1) << 8;
cyrix_did += read_cyrix_reg(DIR0);
} else if (ccr2_test)
cyrix_did = 0x0010; /* 486S A-step */
else
cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
write_eflags(eflags);
}
/*
* Final stage of CPU identification. -- Should I check TI?
*/
void
finishidentcpu(void)
{
if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
if (cpu == CPU_486) {
/*
* These conditions are equivalent to:
* - CPU does not support cpuid instruction.
* - Cyrix/IBM CPU is detected.
*/
if (identblue()) {
strcpy(cpu_vendor, "IBM");
cpu = CPU_BLUE;
return;
}
}
identifycyrix();
/*
* This routine contains a trick.
* Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
*/
switch (cyrix_did & 0x00f0) {
case 0x00:
case 0x10:
case 0xf0:
cpu = CPU_486DLC;
break;
case 0x20:
if ((cyrix_did & 0x00f0) < 8)
cpu = CPU_M1;
else
cpu = CPU_M1SC;
break;
case 0x30:
cpu = CPU_M1;
break;
case 0x40:
cpu = CPU_M1SC;
break;
default:
/* M2 and later CPUs are treated as M2. */
cpu = CPU_M2;
break;
}
}
}
/*
* This routine is called specifically to set up cpu_class before
* startrtclock() uses it. Probably this should be rearranged so that
@ -287,5 +569,6 @@ identifycpu(void)
void
earlysetcpuclass(void)
{
cpu_class = i386_cpus[cpu].cpu_class;
}

173
sys/amd64/amd64/locore.S
View file

@ -34,7 +34,7 @@
* SUCH DAMAGE.
*
* from: @(#)locore.s 7.3 (Berkeley) 5/13/91
* $Id$
* $Id: locore.s,v 1.81 1997/02/22 09:32:22 peter Exp $
*
* originally from: locore.s, by William F. Jolitz
*
@ -192,6 +192,21 @@ _bdb_exists: .long 0
*/
NON_GPROF_ENTRY(btext)
#ifdef PC98
jmp 1f
.globl _pc98_system_parameter
.org 0x400
_pc98_system_parameter:
.space 0x240 /* BIOS parameter block */
1:
/* save SYSTEM PARAMETER for resume (NS/T or other) */
movl $0xa1000,%esi
movl $0x100000,%edi
movl $0x0630,%ecx
cld
rep
movsb
#else /* IBM-PC */
#ifdef BDE_DEBUGGER
#ifdef BIOS_STEALS_3K
cmpl $0x0375c339,0x95504
@ -205,6 +220,7 @@ NON_GPROF_ENTRY(btext)
/* Tell the bios to warmboot next time */
movw $0x1234,0x472
#endif /* PC98 */
/* Set up a real frame in case the double return in newboot is executed. */
pushl %ebp
@ -232,6 +248,28 @@ NON_GPROF_ENTRY(btext)
*/
movl $R(tmpstk),%esp
#ifdef PC98
testb $0x02,0x100620 /* pc98_machine_type & M_EPSON_PC98 */
jz 3f
cmpb $0x0b,0x100624 /* epson_machine_id <= 0x0b */
ja 3f
/* count up memory */
movl $0x100000,%eax /* next, talley remaining memory */
movl $0xFFF-0x100,%ecx
1: movl 0(%eax),%ebx /* save location to check */
movl $0xa55a5aa5,0(%eax) /* write test pattern */
cmpl $0xa55a5aa5,0(%eax) /* does not check yet for rollover */
jne 2f
movl %ebx,0(%eax) /* restore memory */
addl $PAGE_SIZE,%eax
loop 1b
2: subl $0x100000,%eax
shrl $17,%eax
movb %al,0x100401
3:
#endif
call identify_cpu
/* clear bss */
@ -326,7 +364,7 @@ begin:
addl $(13*4),%esp /* back to a frame we can return with */
/*
* now we've run main() and determined what cpu-type we are, we can
* Now we've run main() and determined what cpu-type we are, we can
* enable write protection and alignment checking on i486 cpus and
* above.
*/
@ -524,7 +562,11 @@ olddiskboot:
movl %eax,R(_bootdev)
#if defined(USERCONFIG_BOOT) && defined(USERCONFIG)
#ifdef PC98
movl $0x90200, %esi
#else
movl $0x10200, %esi
#endif
movl $R(_userconfig_from_boot),%edi
movl $512,%ecx
cld
@ -557,11 +599,29 @@ identify_cpu:
popfl
testl %eax,%eax
jnz 1f
jnz try486
/* NexGen CPU does not have aligment check flag. */
pushfl
movl $0x5555, %eax
xorl %edx, %edx
movl $2, %ecx
clc
divl %ecx
jz trynexgen
popfl
movl $CPU_386,R(_cpu)
jmp 3f
1: /* Try to toggle identification flag; does not exist on early 486s. */
trynexgen:
movl $CPU_NX586,R(_cpu)
movl $0x4778654e,R(_cpu_vendor) # store vendor string
movl $0x72446e65,R(_cpu_vendor+4)
movl $0x6e657669,R(_cpu_vendor+8)
movl $0,R(_cpu_vendor+12)
jmp 3f
try486: /* Try to toggle identification flag; does not exist on early 486s. */
pushfl
popl %eax
movl %eax,%ecx
@ -576,89 +636,40 @@ identify_cpu:
popfl
testl %eax,%eax
jnz 1f
jnz trycpuid
movl $CPU_486,R(_cpu)
/* check for Cyrix 486DLC -- based on check routine */
/* documented in "Cx486SLC/e SMM Programmer's Guide" */
xorw %dx,%dx
cmpw %dx,%dx # set flags to known state
pushfw
popw %cx # store flags in ecx
movw $0xffff,%ax
movw $0x0004,%bx
divw %bx
pushfw
popw %ax
andw $0x08d5,%ax # mask off important bits
andw $0x08d5,%cx
cmpw %ax,%cx
/*
* Check Cyrix CPU
* Cyrix CPUs do not change the undefined flags following
* execution of the divide instruction which divides 5 by 2.
*
* Note: CPUID is enabled on M2, so it passes another way.
*/
pushfl
movl $0x5555, %eax
xorl %edx, %edx
movl $2, %ecx
clc
divl %ecx
jnc trycyrix
popfl
jmp 3f /* You may use Intel CPU. */
jnz 3f # if flags changed, Intel chip
movl $CPU_486DLC,R(_cpu) # set CPU value for Cyrix
trycyrix:
popfl
/*
* IBM Bluelighting CPU also doesn't change the undefined flags.
* Because IBM doesn't disclose the information for Bluelighting
* CPU, we couldn't distinguish it from Cyrix's (including IBM
* brand of Cyrix CPUs).
*/
movl $0x69727943,R(_cpu_vendor) # store vendor string
movw $0x0078,R(_cpu_vendor+4)
#ifndef CYRIX_CACHE_WORKS
/* Disable caching of the ISA hole only. */
invd
movb $CCR0,%al # Configuration Register index (CCR0)
outb %al,$0x22
inb $0x23,%al
orb $(CCR0_NC1|CCR0_BARB),%al
movb %al,%ah
movb $CCR0,%al
outb %al,$0x22
movb %ah,%al
outb %al,$0x23
invd
#else /* CYRIX_CACHE_WORKS */
/* Set cache parameters */
invd # Start with guaranteed clean cache
movb $CCR0,%al # Configuration Register index (CCR0)
outb %al,$0x22
inb $0x23,%al
andb $~CCR0_NC0,%al
#ifndef CYRIX_CACHE_REALLY_WORKS
orb $(CCR0_NC1|CCR0_BARB),%al
#else /* CYRIX_CACHE_REALLY_WORKS */
orb $CCR0_NC1,%al
#endif /* !CYRIX_CACHE_REALLY_WORKS */
movb %al,%ah
movb $CCR0,%al
outb %al,$0x22
movb %ah,%al
outb %al,$0x23
/* clear non-cacheable region 1 */
movb $(NCR1+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* clear non-cacheable region 2 */
movb $(NCR2+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* clear non-cacheable region 3 */
movb $(NCR3+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* clear non-cacheable region 4 */
movb $(NCR4+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* enable caching in CR0 */
movl %cr0,%eax
andl $~(CR0_CD|CR0_NW),%eax
movl %eax,%cr0
invd
#endif /* !CYRIX_CACHE_WORKS */
movl $0x736e4978,R(_cpu_vendor+4)
movl $0x64616574,R(_cpu_vendor+8)
jmp 3f
1: /* Use the `cpuid' instruction. */
trycpuid: /* Use the `cpuid' instruction. */
xorl %eax,%eax
.byte 0x0f,0xa2 # cpuid 0
movl %eax,R(_cpu_high) # highest capability

173
sys/amd64/amd64/locore.s
View file

@ -34,7 +34,7 @@
* SUCH DAMAGE.
*
* from: @(#)locore.s 7.3 (Berkeley) 5/13/91
* $Id$
* $Id: locore.s,v 1.81 1997/02/22 09:32:22 peter Exp $
*
* originally from: locore.s, by William F. Jolitz
*
@ -192,6 +192,21 @@ _bdb_exists: .long 0
*/
NON_GPROF_ENTRY(btext)
#ifdef PC98
jmp 1f
.globl _pc98_system_parameter
.org 0x400
_pc98_system_parameter:
.space 0x240 /* BIOS parameter block */
1:
/* save SYSTEM PARAMETER for resume (NS/T or other) */
movl $0xa1000,%esi
movl $0x100000,%edi
movl $0x0630,%ecx
cld
rep
movsb
#else /* IBM-PC */
#ifdef BDE_DEBUGGER
#ifdef BIOS_STEALS_3K
cmpl $0x0375c339,0x95504
@ -205,6 +220,7 @@ NON_GPROF_ENTRY(btext)
/* Tell the bios to warmboot next time */
movw $0x1234,0x472
#endif /* PC98 */
/* Set up a real frame in case the double return in newboot is executed. */
pushl %ebp
@ -232,6 +248,28 @@ NON_GPROF_ENTRY(btext)
*/
movl $R(tmpstk),%esp
#ifdef PC98
testb $0x02,0x100620 /* pc98_machine_type & M_EPSON_PC98 */
jz 3f
cmpb $0x0b,0x100624 /* epson_machine_id <= 0x0b */
ja 3f
/* count up memory */
movl $0x100000,%eax /* next, talley remaining memory */
movl $0xFFF-0x100,%ecx
1: movl 0(%eax),%ebx /* save location to check */
movl $0xa55a5aa5,0(%eax) /* write test pattern */
cmpl $0xa55a5aa5,0(%eax) /* does not check yet for rollover */
jne 2f
movl %ebx,0(%eax) /* restore memory */
addl $PAGE_SIZE,%eax
loop 1b
2: subl $0x100000,%eax
shrl $17,%eax
movb %al,0x100401
3:
#endif
call identify_cpu
/* clear bss */
@ -326,7 +364,7 @@ begin:
addl $(13*4),%esp /* back to a frame we can return with */
/*
* now we've run main() and determined what cpu-type we are, we can
* Now we've run main() and determined what cpu-type we are, we can
* enable write protection and alignment checking on i486 cpus and
* above.
*/
@ -524,7 +562,11 @@ olddiskboot:
movl %eax,R(_bootdev)
#if defined(USERCONFIG_BOOT) && defined(USERCONFIG)
#ifdef PC98
movl $0x90200, %esi
#else
movl $0x10200, %esi
#endif
movl $R(_userconfig_from_boot),%edi
movl $512,%ecx
cld
@ -557,11 +599,29 @@ identify_cpu:
popfl
testl %eax,%eax
jnz 1f
jnz try486
/* NexGen CPU does not have aligment check flag. */
pushfl
movl $0x5555, %eax
xorl %edx, %edx
movl $2, %ecx
clc
divl %ecx
jz trynexgen
popfl
movl $CPU_386,R(_cpu)
jmp 3f
1: /* Try to toggle identification flag; does not exist on early 486s. */
trynexgen:
movl $CPU_NX586,R(_cpu)
movl $0x4778654e,R(_cpu_vendor) # store vendor string
movl $0x72446e65,R(_cpu_vendor+4)
movl $0x6e657669,R(_cpu_vendor+8)
movl $0,R(_cpu_vendor+12)
jmp 3f
try486: /* Try to toggle identification flag; does not exist on early 486s. */
pushfl
popl %eax
movl %eax,%ecx
@ -576,89 +636,40 @@ identify_cpu:
popfl
testl %eax,%eax
jnz 1f
jnz trycpuid
movl $CPU_486,R(_cpu)
/* check for Cyrix 486DLC -- based on check routine */
/* documented in "Cx486SLC/e SMM Programmer's Guide" */
xorw %dx,%dx
cmpw %dx,%dx # set flags to known state
pushfw
popw %cx # store flags in ecx
movw $0xffff,%ax
movw $0x0004,%bx
divw %bx
pushfw
popw %ax
andw $0x08d5,%ax # mask off important bits
andw $0x08d5,%cx
cmpw %ax,%cx
/*
* Check Cyrix CPU
* Cyrix CPUs do not change the undefined flags following
* execution of the divide instruction which divides 5 by 2.
*
* Note: CPUID is enabled on M2, so it passes another way.
*/
pushfl
movl $0x5555, %eax
xorl %edx, %edx
movl $2, %ecx
clc
divl %ecx
jnc trycyrix
popfl
jmp 3f /* You may use Intel CPU. */
jnz 3f # if flags changed, Intel chip
movl $CPU_486DLC,R(_cpu) # set CPU value for Cyrix
trycyrix:
popfl
/*
* IBM Bluelighting CPU also doesn't change the undefined flags.
* Because IBM doesn't disclose the information for Bluelighting
* CPU, we couldn't distinguish it from Cyrix's (including IBM
* brand of Cyrix CPUs).
*/
movl $0x69727943,R(_cpu_vendor) # store vendor string
movw $0x0078,R(_cpu_vendor+4)
#ifndef CYRIX_CACHE_WORKS
/* Disable caching of the ISA hole only. */
invd
movb $CCR0,%al # Configuration Register index (CCR0)
outb %al,$0x22
inb $0x23,%al
orb $(CCR0_NC1|CCR0_BARB),%al
movb %al,%ah
movb $CCR0,%al
outb %al,$0x22
movb %ah,%al
outb %al,$0x23
invd
#else /* CYRIX_CACHE_WORKS */
/* Set cache parameters */
invd # Start with guaranteed clean cache
movb $CCR0,%al # Configuration Register index (CCR0)
outb %al,$0x22
inb $0x23,%al
andb $~CCR0_NC0,%al
#ifndef CYRIX_CACHE_REALLY_WORKS
orb $(CCR0_NC1|CCR0_BARB),%al
#else /* CYRIX_CACHE_REALLY_WORKS */
orb $CCR0_NC1,%al
#endif /* !CYRIX_CACHE_REALLY_WORKS */
movb %al,%ah
movb $CCR0,%al
outb %al,$0x22
movb %ah,%al
outb %al,$0x23
/* clear non-cacheable region 1 */
movb $(NCR1+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* clear non-cacheable region 2 */
movb $(NCR2+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* clear non-cacheable region 3 */
movb $(NCR3+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* clear non-cacheable region 4 */
movb $(NCR4+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* enable caching in CR0 */
movl %cr0,%eax
andl $~(CR0_CD|CR0_NW),%eax
movl %eax,%cr0
invd
#endif /* !CYRIX_CACHE_WORKS */
movl $0x736e4978,R(_cpu_vendor+4)
movl $0x64616574,R(_cpu_vendor+8)
jmp 3f
1: /* Use the `cpuid' instruction. */
trycpuid: /* Use the `cpuid' instruction. */
xorl %eax,%eax
.byte 0x0f,0xa2 # cpuid 0
movl %eax,R(_cpu_high) # highest capability

14
sys/amd64/amd64/machdep.c
View file

@ -35,7 +35,7 @@
* SUCH DAMAGE.
*
* from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
* $Id: machdep.c,v 1.228 1997/02/22 09:32:26 peter Exp $
* $Id: machdep.c,v 1.229 1997/02/24 00:37:43 alex Exp $
*/
#include "npx.h"
@ -122,8 +122,11 @@ extern int ptrace_single_step __P((struct proc *p));
extern int ptrace_write_u __P((struct proc *p, vm_offset_t off, int data));
extern void dblfault_handler __P((void));
extern void identifycpu(void); /* XXX header file */
extern void printcpuinfo(void); /* XXX header file */
extern void earlysetcpuclass(void); /* same header file */
extern void finishidentcpu(void);
extern void panicifcpuunsupported(void);
extern void initializecpu(void);
static void cpu_startup __P((void *));
SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
@ -208,7 +211,8 @@ cpu_startup(dummy)
printf(version);
earlysetcpuclass();
startrtclock();
identifycpu();
printcpuinfo();
panicifcpuunsupported();
#ifdef PERFMON
perfmon_init();
#endif
@ -1059,6 +1063,10 @@ init386(first)
Debugger("Boot flags requested debugger");
#endif
finishidentcpu(); /* Final stage of CPU initialization */
setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
initializecpu(); /* Initialize CPU registers */
/* Use BIOS values stored in RTC CMOS RAM, since probing
* breaks certain 386 AT relics.
*/

16
sys/amd64/include/cpufunc.h
View file

@ -30,7 +30,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
* $Id: cpufunc.h,v 1.61 1997/02/22 09:34:08 peter Exp $
*/
/*
@ -195,6 +195,12 @@ insl(u_int port, void *addr, size_t cnt)
: "di", "cx", "memory");
}
static __inline void
invd(void)
{
__asm __volatile("invd");
}
static __inline void
invlpg(u_int addr)
{
@ -338,6 +344,12 @@ setbits(volatile unsigned *addr, u_int bits)
__asm __volatile("orl %1,%0" : "=m" (*addr) : "ir" (bits));
}
static __inline void
wbinvd(void)
{
__asm __volatile("wbinvd");
}
static __inline void
write_eflags(u_long ef)
{
@ -360,6 +372,7 @@ u_long inl __P((u_int port));
void insb __P((u_int port, void *addr, size_t cnt));
void insl __P((u_int port, void *addr, size_t cnt));
void insw __P((u_int port, void *addr, size_t cnt));
void invd __P((void));
void invlpg __P((u_int addr));
void invltlb __P((void));
u_short inw __P((u_int port));
@ -376,6 +389,7 @@ quad_t rdpmc __P((u_int pmc));
quad_t rdtsc __P((void));
u_long read_eflags __P((void));
void setbits __P((volatile unsigned *addr, u_int bits));
void wbinvd __P((void));
void write_eflags __P((u_long ef));
void wrmsr __P((u_int msr, quad_t newval));

8
sys/amd64/include/cputypes.h
View file

@ -24,7 +24,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id$
* $Id: cputypes.h,v 1.7 1997/02/22 09:34:14 peter Exp $
*/
#ifndef _MACHINE_CPUTYPES_H_
@ -52,5 +52,9 @@
#define CPU_586 5 /* Intel P.....m (I hate lawyers; it's TM) */
#define CPU_486DLC 6 /* Cyrix 486DLC */
#define CPU_686 7 /* Pentium Pro */
#define CPU_M1SC 8 /* Cyrix M1sc (aka 5x86) */
#define CPU_M1 9 /* Cyrix M1 (aka 6x86) */
#define CPU_BLUE 10 /* IBM BlueLighting CPU */
#define CPU_M2 11 /* Cyrix M2 (aka enhanced 6x86 with MMX */
#define CPU_NX586 12 /* NexGen (now AMD) 586 */
#endif /* _MACHINE_CPUTYPES_H_ */

8
sys/amd64/include/md_var.h
View file

@ -26,7 +26,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
* $Id: md_var.h,v 1.12 1997/02/22 09:34:49 peter Exp $
*/
#ifndef _MACHINE_MD_VAR_H_
@ -41,6 +41,7 @@ extern u_int atdevbase; /* offset in virtual memory of ISA io mem */
extern u_long cpu_feature;
extern u_long cpu_high;
extern u_long cpu_id;
extern u_long cyrix_did;
extern char cpu_vendor[];
extern char etext[];
extern char kstack[];
@ -72,4 +73,9 @@ void userconfig __P((void));
void vm_bounce_init __P((void));
int vm_page_zero_idle __P((void));
#ifdef PC98
extern int need_pre_dma_flush;
extern int need_post_dma_flush;
#endif
#endif /* !_MACHINE_MD_VAR_H_ */

212
sys/amd64/include/specialreg.h
View file

@ -31,7 +31,7 @@
* SUCH DAMAGE.
*
* from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
* $Id$
* $Id: specialreg.h,v 1.12 1997/02/22 09:35:15 peter Exp $
*/
#ifndef _MACHINE_SPECIALREG_H_
@ -54,11 +54,12 @@
/*
* Bits in 486 special registers:
*/
#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
#define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */
#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
#define CR0_NW 0x20000000 /* Not Write-through */
#define CR0_CD 0x40000000 /* Cache Disable */
#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
#define CR0_WP 0x00010000 /* Write Protect (honor page protect in
all modes) */
#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
#define CR0_NW 0x20000000 /* Not Write-through */
#define CR0_CD 0x40000000 /* Cache Disable */
/*
* Bits in PPro special registers
@ -94,26 +95,81 @@
#define CPUID_CMOV 0x8000
/*
* Cyrix 486 DLC special registers, accessible as IO ports.
* Cyrix configuration registers, accessible as IO ports.
*/
#define CCR0 0xc0 /* configuration control register 0 */
#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is
non-cacheable */
#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
#define CCR0_A20M 0x04 /* enables A20M# input pin */
#define CCR0_KEN 0x08 /* enables KEN# input pin */
#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
#define CCR0_BARB 0x20 /* flushes internal cache when entering hold
state */
#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
#define CCR0 0xc0 /* Configuration control register 0 */
#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
non-cacheable */
#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
#define CCR0_A20M 0x04 /* Enables A20M# input pin */
#define CCR0_KEN 0x08 /* Enables KEN# input pin */
#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
state */
#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
assoc */
#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
#define CCR1 0xc1 /* configuration control register 1 */
#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
/* the remaining 7 bits of this register are reserved */
#define CCR1 0xc1 /* Configuration control register 1 */
#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
#define CCR1_SMI 0x02 /* Enables SMM pins */
#define CCR1_SMAC 0x04 /* System management memory access */
#define CCR1_MMAC 0x08 /* Main memory access */
#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
#define CCR1_SM3 0x80 /* SMM address space address region 3 */
#define CCR2 0xc2
#define CCR2_WB 0x02 /* Enables WB cache interface pins */
#define CCR2_SADS 0x02 /* Slow ADS */
#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
#define CCR2_WT1 0x10 /* WT region 1 */
#define CCR2_WPR1 0x10 /* Write-protect region 1 */
#define CCR2_BARB 0x20 /* Flushes write-back cache when entering
hold state. */
#define CCR2_BWRT 0x40 /* Enables burst write cycles */
#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
#define CCR3 0xc3
#define CCR3_SMILOCK 0x01 /* SMM register lock */
#define CCR3_NMI 0x02 /* Enables NMI during SMM */
#define CCR3_LINBRST 0x04 /* Linear address burst cycles */
#define CCR3_SMMMODE 0x08 /* SMM Mode */
#define CCR3_MAPEN0 0x10 /* Enables Map0 */
#define CCR3_MAPEN1 0x20 /* Enables Map1 */
#define CCR3_MAPEN2 0x40 /* Enables Map2 */
#define CCR3_MAPEN3 0x80 /* Enables Map3 */
#define CCR4 0xe8
#define CCR4_IOMASK 0x07
#define CCR4_MEM 0x08 /* Enables momory bypassing */
#define CCR4_DTE 0x10 /* Enables directory table entry cache */
#define CCR4_FASTFPE 0x20 /* Fast FPU exception */
#define CCR4_CPUID 0x80 /* Enables CPUID instruction */
#define CCR5 0xe9
#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
#define CCR5_LBR1 0x10 /* Local bus region 1 */
#define CCR5_ARREN 0x20 /* Enables ARR region */
/* Performance Control Register (5x86 only). */
#define PCR0 0x20
#define PCR0_RSTK 0x01 /* Enables return stack */
#define PCR0_BTB 0x02 /* Enables branch target buffer */
#define PCR0_LOOP 0x04 /* Enables loop */
#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
serialize pipe. */
#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
#define PCR0_BTBRT 0x40 /* Enables BTB test register. */
#define PCR0_LSSER 0x80 /* Disable reorder */
/* Device Identification Registers */
#define DIR0 0xfe
#define DIR1 0xff
/*
* the following four 3-byte registers control the non-cacheable regions.
* The following four 3-byte registers control the non-cacheable regions.
* These registers must be written as three separate bytes.
*
* NCRx+0: A31-A24 of starting address
@ -123,26 +179,98 @@
* The non-cacheable region's starting address must be aligned to the
* size indicated by the NCR_SIZE_xx field.
*/
#define NCR1 0xc4
#define NCR2 0xc7
#define NCR3 0xca
#define NCR4 0xcd
#define NCR1 0xc4
#define NCR2 0xc7
#define NCR3 0xca
#define NCR4 0xcd
#define NCR_SIZE_0K 0
#define NCR_SIZE_4K 1
#define NCR_SIZE_8K 2
#define NCR_SIZE_16K 3
#define NCR_SIZE_32K 4
#define NCR_SIZE_64K 5
#define NCR_SIZE_128K 6
#define NCR_SIZE_256K 7
#define NCR_SIZE_512K 8
#define NCR_SIZE_1M 9
#define NCR_SIZE_2M 10
#define NCR_SIZE_4M 11
#define NCR_SIZE_8M 12
#define NCR_SIZE_16M 13
#define NCR_SIZE_32M 14
#define NCR_SIZE_4G 15
#define NCR_SIZE_0K 0
#define NCR_SIZE_4K 1
#define NCR_SIZE_8K 2
#define NCR_SIZE_16K 3
#define NCR_SIZE_32K 4
#define NCR_SIZE_64K 5
#define NCR_SIZE_128K 6
#define NCR_SIZE_256K 7
#define NCR_SIZE_512K 8
#define NCR_SIZE_1M 9
#define NCR_SIZE_2M 10
#define NCR_SIZE_4M 11
#define NCR_SIZE_8M 12
#define NCR_SIZE_16M 13
#define NCR_SIZE_32M 14
#define NCR_SIZE_4G 15
/*
* The address region registers are used to specify the location and
* size for the eight address regions.
*
* ARRx + 0: A31-A24 of start address
* ARRx + 1: A23-A16 of start address
* ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
*/
#define ARR0 0xc4
#define ARR1 0xc7
#define ARR2 0xca
#define ARR3 0xcd
#define ARR4 0xd0
#define ARR5 0xd3
#define ARR6 0xd6
#define ARR7 0xd9
#define ARR_SIZE_0K 0
#define ARR_SIZE_4K 1
#define ARR_SIZE_8K 2
#define ARR_SIZE_16K 3
#define ARR_SIZE_32K 4
#define ARR_SIZE_64K 5
#define ARR_SIZE_128K 6
#define ARR_SIZE_256K 7
#define ARR_SIZE_512K 8
#define ARR_SIZE_1M 9
#define ARR_SIZE_2M 10
#define ARR_SIZE_4M 11
#define ARR_SIZE_8M 12
#define ARR_SIZE_16M 13
#define ARR_SIZE_32M 14
#define ARR_SIZE_4G 15
/*
* The region control registers specify the attributes associated with
* the ARRx addres regions.
*/
#define RCR0 0xdc
#define RCR1 0xdd
#define RCR2 0xde
#define RCR3 0xdf
#define RCR4 0xe0
#define RCR5 0xe1
#define RCR6 0xe2
#define RCR7 0xe3
#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
#define RCR_RCE 0x01 /* Enables caching for ARR7. */
#define RCR_WWO 0x02 /* Weak write ordering. */
#define RCR_WL 0x04 /* Weak locking. */
#define RCR_WG 0x08 /* Write gathering. */
#define RCR_WT 0x10 /* Write-through. */
#define RCR_NLB 0x20 /* LBA# pin is not asserted. */
#ifndef LOCORE
static __inline u_char
read_cyrix_reg(u_char reg)
{
outb(0x22, reg);
return inb(0x23);
}
static __inline void
write_cyrix_reg(u_char reg, u_char data)
{
outb(0x22, reg);
outb(0x23, data);
}
#endif
#endif /* !_MACHINE_SPECIALREG_H_ */

8
sys/conf/Makefile.pc98
View file

@ -3,7 +3,7 @@
# Makefile.i386 -- with config changes.
# Copyright 1990 W. Jolitz
# from: @(#)Makefile.i386 7.1 5/10/91
# $Id$
# $Id: Makefile.pc98,v 1.11 1997/02/22 09:43:21 peter Exp $
#
# Makefile for FreeBSD
#
@ -58,7 +58,7 @@ DRIVER_S= ${CC} -c -x assembler-with-cpp -DLOCORE ${COPTS} $<
PROFILE_C= ${CC} -c ${CFLAGS} ${PARAM} $<
SYSTEM_CFILES= ioconf.c param.c vnode_if.c config.c
SYSTEM_SFILES= ${PC98}/i386/locore.s
SYSTEM_SFILES= ${I386}/i386/locore.s
SYSTEM_OBJS= locore.o vnode_if.o ${OBJS} ioconf.o param.o config.o
SYSTEM_DEP= Makefile symbols.exclude symbols.sort ${SYSTEM_OBJS}
SYSTEM_LD_HEAD= @echo loading $@; rm -f $@
@ -89,7 +89,7 @@ clean:
#lint: /tmp param.c
# @lint -hbxn -DGENERIC -Dvolatile= ${COPTS} ${PARAM} \
# ${PC98}/i386/Locore.c ${CFILES} ioconf.c param.c | \
# ${I386}/i386/Locore.c ${CFILES} ioconf.c param.c | \
# grep -v 'struct/union .* never defined' | \
# grep -v 'possible pointer alignment problem'
@ -101,7 +101,7 @@ symbols.sort: ${I386}/i386/symbols.raw
grep -v '^#' ${I386}/i386/symbols.raw \
| sed 's/^ //' | sort -u > symbols.sort
locore.o: ${PC98}/i386/locore.s assym.s
locore.o: ${I386}/i386/locore.s assym.s
${NORMAL_S}
# everything potentially depends on the Makefile since everything potentially

3
sys/conf/files.i386
View file

@ -1,7 +1,7 @@
# This file tells config what files go into building a kernel,
# files marked standard are always included.
#
# $Id: files.i386,v 1.155 1997/03/16 07:09:01 gibbs Exp $
# $Id: files.i386,v 1.156 1997/03/16 17:25:53 bde Exp $
#
aic7xxx_asm optional ahc device-driver \
dependency "$S/dev/aic7xxx/*.[chyl]" \
@ -47,6 +47,7 @@ i386/i386/i386-gdbstub.c optional ddb
i386/i386/exception.s standard
i386/i386/identcpu.c standard
i386/i386/in_cksum.c optional inet
i386/i386/initcpu.c standard
# locore.s needs to be handled in Makefile to put it first. Otherwise it's
# now normal.
# i386/i386/locore.s standard

3
sys/conf/files.pc98
View file

@ -3,7 +3,7 @@
#
# modified for PC-9801
#
# $Id: files.pc98,v 1.16 1997/02/22 09:43:22 peter Exp $
# $Id: files.pc98,v 1.17 1997/03/19 16:14:25 kato Exp $
#
aic7xxx_asm optional ahc device-driver \
dependency "$S/dev/aic7xxx/*.[chyl]" \
@ -49,6 +49,7 @@ i386/i386/i386-gdbstub.c optional ddb
i386/i386/exception.s standard
i386/i386/identcpu.c standard
i386/i386/in_cksum.c optional inet
i386/i386/initcpu.c standard
# locore.s needs to be handled in Makefile to put it first. Otherwise it's
# now normal.
# i386/i386/locore.s standard

23
sys/conf/options.i386
View file

@ -1,4 +1,4 @@
# $Id: options.i386,v 1.36 1997/02/28 16:56:06 bde Exp $
# $Id: options.i386,v 1.37 1997/03/12 17:41:35 joerg Exp $
BOUNCEPAGES opt_bounce.h
USER_LDT
MATH_EMULATE opt_math_emulate.h
@ -37,10 +37,23 @@ CLK_CALIBRATION_LOOP opt_clock.h
CLK_USE_I8254_CALIBRATION opt_clock.h
CLK_USE_I586_CALIBRATION opt_clock.h
I386_CPU opt_cpu.h
I486_CPU opt_cpu.h
I586_CPU opt_cpu.h
I686_CPU opt_cpu.h
CPU_BLUELIGHTNING_FPU_OP_CACHE opt_cpu.h
CPU_BLUELIGHTNING_3X opt_cpu.h
CPU_BTB_EN opt_cpu.h
CPU_DISABLE_5X86_LSSER opt_cpu.h
CPU_FASTER_5X86_FPU opt_cpu.h
CPU_I486_ON_386 opt_cpu.h
CPU_IORT opt_cpu.h
CPU_LOOP_EN opt_cpu.h
CPU_RSTK_EN opt_cpu.h
CPU_SUSP_HLT opt_cpu.h
CPU_UPGRADE_HW_CACHE opt_cpu.h
CYRIX_CACHE_WORKS opt_cpu.h
CYRIX_CACHE_REALLY_WORKS opt_cpu.h
I386_CPU opt_cpu.h
I486_CPU opt_cpu.h
I586_CPU opt_cpu.h
I686_CPU opt_cpu.h
SC_SPLASH_SCREEN opt_syscons.h
MAXCONS opt_syscons.h

21
sys/conf/options.pc98
View file

@ -1,4 +1,4 @@
# $Id: options.pc98,v 1.17 1997/03/01 11:06:41 kato Exp $
# $Id: options.pc98,v 1.18 1997/03/13 17:04:23 kato Exp $
BOUNCEPAGES opt_bounce.h
USER_LDT
MATH_EMULATE opt_math_emulate.h
@ -37,10 +37,21 @@ CLK_CALIBRATION_LOOP opt_clock.h
CLK_USE_I8254_CALIBRATION opt_clock.h
CLK_USE_I586_CALIBRATION opt_clock.h
I386_CPU opt_cpu.h
I486_CPU opt_cpu.h
I586_CPU opt_cpu.h
I686_CPU opt_cpu.h
CPU_BTB_EN opt_cpu.h
CPU_DISABLE_5X86_LSSER opt_cpu.h
CPU_FASTER_5X86_FPU opt_cpu.h
CPU_I486_ON_386 opt_cpu.h
CPU_IORT opt_cpu.h
CPU_LOOP_EN opt_cpu.h
CPU_RSTK_EN opt_cpu.h
CPU_SUSP_HLT opt_cpu.h
CPU_UPGRADE_HW_CACHE opt_cpu.h
CYRIX_CACHE_WORKS opt_cpu.h
CYRIX_CACHE_REALLY_WORKS opt_cpu.h
I386_CPU opt_cpu.h
I486_CPU opt_cpu.h
I586_CPU opt_cpu.h
I686_CPU opt_cpu.h
SC_SPLASH_SCREEN opt_syscons.h
MAXCONS opt_syscons.h

3
sys/i386/conf/files.i386
View file

@ -1,7 +1,7 @@
# This file tells config what files go into building a kernel,
# files marked standard are always included.
#
# $Id: files.i386,v 1.155 1997/03/16 07:09:01 gibbs Exp $
# $Id: files.i386,v 1.156 1997/03/16 17:25:53 bde Exp $
#
aic7xxx_asm optional ahc device-driver \
dependency "$S/dev/aic7xxx/*.[chyl]" \
@ -47,6 +47,7 @@ i386/i386/i386-gdbstub.c optional ddb
i386/i386/exception.s standard
i386/i386/identcpu.c standard
i386/i386/in_cksum.c optional inet
i386/i386/initcpu.c standard
# locore.s needs to be handled in Makefile to put it first. Otherwise it's
# now normal.
# i386/i386/locore.s standard

23
sys/i386/conf/options.i386
View file

@ -1,4 +1,4 @@
# $Id: options.i386,v 1.36 1997/02/28 16:56:06 bde Exp $
# $Id: options.i386,v 1.37 1997/03/12 17:41:35 joerg Exp $
BOUNCEPAGES opt_bounce.h
USER_LDT
MATH_EMULATE opt_math_emulate.h
@ -37,10 +37,23 @@ CLK_CALIBRATION_LOOP opt_clock.h
CLK_USE_I8254_CALIBRATION opt_clock.h
CLK_USE_I586_CALIBRATION opt_clock.h
I386_CPU opt_cpu.h
I486_CPU opt_cpu.h
I586_CPU opt_cpu.h
I686_CPU opt_cpu.h
CPU_BLUELIGHTNING_FPU_OP_CACHE opt_cpu.h
CPU_BLUELIGHTNING_3X opt_cpu.h
CPU_BTB_EN opt_cpu.h
CPU_DISABLE_5X86_LSSER opt_cpu.h
CPU_FASTER_5X86_FPU opt_cpu.h
CPU_I486_ON_386 opt_cpu.h
CPU_IORT opt_cpu.h
CPU_LOOP_EN opt_cpu.h
CPU_RSTK_EN opt_cpu.h
CPU_SUSP_HLT opt_cpu.h
CPU_UPGRADE_HW_CACHE opt_cpu.h
CYRIX_CACHE_WORKS opt_cpu.h
CYRIX_CACHE_REALLY_WORKS opt_cpu.h
I386_CPU opt_cpu.h
I486_CPU opt_cpu.h
I586_CPU opt_cpu.h
I686_CPU opt_cpu.h
SC_SPLASH_SCREEN opt_syscons.h
MAXCONS opt_syscons.h

297
sys/i386/i386/identcpu.c
View file

@ -1,6 +1,7 @@
/*-
/*
* Copyright (c) 1992 Terrence R. Lambert.
* Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
* Copyright (c) 1997 KATO Takenori.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
@ -35,7 +36,7 @@
* SUCH DAMAGE.
*
* from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
* $Id$
* $Id: identcpu.c,v 1.13 1997/02/22 09:32:19 peter Exp $
*/
#include "opt_cpu.h"
@ -54,12 +55,18 @@
#include <machine/sysarch.h>
#include <machine/md_var.h>
#include <i386/isa/isa_device.h>
/* XXX - should be in header file */
void i486_bzero __P((void *buf, size_t len));
void identifycpu(void); /* XXX should be in different header file */
void printcpuinfo(void); /* XXX should be in different header file */
void finishidentcpu(void);
void earlysetcpuclass(void);
void panicifcpuunsupported(void);
static void identifycyrix(void);
u_long cyrix_did; /* Device ID of Cyirx CPU */
int cpu_class = CPUCLASS_386; /* least common denominator */
char machine[] = "i386";
SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
@ -74,13 +81,19 @@ static struct cpu_nameclass i386_cpus[] = {
{ "i486SX", CPUCLASS_486 }, /* CPU_486SX */
{ "i486DX", CPUCLASS_486 }, /* CPU_486 */
{ "Pentium", CPUCLASS_586 }, /* CPU_586 */
{ "Cy486DLC", CPUCLASS_486 }, /* CPU_486DLC */
{ "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
{ "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
{ "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
{ "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
{ "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
{ "Cyrix 6x86 MMX", CPUCLASS_586 }, /* CPU_M2 (XXX) */
{ "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
};
void
identifycpu(void)
printcpuinfo(void)
{
cpu_class = i386_cpus[cpu].cpu_class;
printf("CPU: ");
strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof cpu_model);
@ -140,7 +153,6 @@ identifycpu(void)
* Values taken from AMD Processor Recognition
* http://www.amd.com/html/products/pcd/techdocs/appnotes/20734c.pdf
*/
cpu_model[0] = '\0';
strcpy(cpu_model, "AMD ");
switch (cpu_id & 0xFF0) {
case 0x4E0:
@ -162,8 +174,119 @@ identifycpu(void)
strcat(cpu_model, "Unknown");
break;
}
}
} else if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
strcpy(cpu_model, "Cyrix ");
switch (cyrix_did & 0xf0) {
case 0x00:
switch (cyrix_did & 0x0f) {
case 0x00:
strcat(cpu_model, "486SLC");
break;
case 0x01:
strcat(cpu_model, "486DLC");
break;
case 0x02:
strcat(cpu_model, "486SLC2");
break;
case 0x03:
strcat(cpu_model, "486DLC2");
break;
case 0x04:
strcat(cpu_model, "486SRx");
break;
case 0x05:
strcat(cpu_model, "486DRx");
break;
case 0x06:
strcat(cpu_model, "486SRx2");
break;
case 0x07:
strcat(cpu_model, "486DRx2");
break;
case 0x08:
strcat(cpu_model, "486SRu");
break;
case 0x09:
strcat(cpu_model, "486DRu");
break;
case 0x0a:
strcat(cpu_model, "486SRu2");
break;
case 0x0b:
strcat(cpu_model, "486DRu2");
break;
default:
strcat(cpu_model, "Unknown");
break;
}
break;
case 0x10:
switch (cyrix_did & 0x0f) {
case 0x00:
strcat(cpu_model, "486S");
break;
case 0x01:
strcat(cpu_model, "486S2");
break;
case 0x02:
strcat(cpu_model, "486Se");
break;
case 0x03:
strcat(cpu_model, "486S2e");
break;
case 0x0a:
strcat(cpu_model, "486DX");
break;
case 0x0b:
strcat(cpu_model, "486DX2");
break;
case 0x0f:
strcat(cpu_model, "486DX4");
break;
default:
strcat(cpu_model, "Unknown");
break;
}
break;
case 0x20:
if ((cyrix_did & 0x0f) < 8)
strcat(cpu_model, "6x86"); /* Where did you get it? */
else
strcat(cpu_model, "5x86");
break;
case 0x30:
strcat(cpu_model, "6x86");
break;
case 0x40:
/* XXX */
strcat(cpu_model, "Gx86");
break;
case 0x50:
strcat(cpu_model, "Enhanced 6x86 with MMX");
break;
case 0xf0:
switch (cyrix_did & 0x0f) {
case 0x0d:
strcat(cpu_model, "Overdrive CPU");
case 0x0e:
strcpy(cpu_model, "Texas Instruments 486SXL");
break;
case 0x0f:
strcat(cpu_model, "486SLC/DLC");
break;
default:
strcat(cpu_model, "Unknown");
break;
}
break;
default:
strcat(cpu_model, "Unknown");
break;
}
} else if (strcmp(cpu_vendor,"IBM") == 0)
strcpy(cpu_model, "Blue Lightning CPU");
#endif
printf("%s (", cpu_model);
switch(cpu_class) {
case CPUCLASS_286:
@ -238,6 +361,14 @@ identifycpu(void)
"\020CMOV"
);
}
} else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
printf(" Device ID = 0x%lx", cyrix_did);
printf(" Stepping=%ld", (cyrix_did & 0xf000) >> 12);
printf(" Revision=%ld", (cyrix_did & 0x0fff) >> 8);
#ifndef CYRIX_CACHE_REALLY_WORKS
if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
printf("\n CPU cache: write-through mode");
#endif
}
/* Avoid ugly blank lines: only print newline when we have to. */
if (*cpu_vendor || cpu_id)
@ -248,6 +379,11 @@ identifycpu(void)
* XXX - Do PPro CPUID level=2 stuff here?
*/
#endif
}
void
panicifcpuunsupported(void)
{
/*
* Now that we have told the user what they have,
@ -276,6 +412,152 @@ identifycpu(void)
}
}
static volatile u_int trap_by_wrmsr;
/*
* Special exception 16 handler.
* The wrmsr instruction generates invalid opcodes fault on 486-class
* Cyrix CPU. Stacked eip register points the wrmsr instruction in the
* function identblue() when this handler is called. Stacked eip should
* be advanced.
*/
inthand_t bluetrap;
asm
("
.text
_bluetrap:
ss
movl $0xa8c1d, _trap_by_wrmsr # Don't ask meaning of the number :-).
addl $2, (%esp) # I know wrmsr is a 2-bytes instruction.
iret
");
/*
* Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
* support cpuid instruction. This function should be called after
* loading interrupt descriptor table register.
*
* I don't like this method that handles fault, but I couldn't get
* information for any other methods. Does blue giant know?
*/
static int
identblue(void)
{
trap_by_wrmsr = 0;
/*
* Cyrix 486-class CPU does not support wrmsr instruction.
* The wrmsr instruction causes invalid opcode fault, and exception
* will be trapped by bluetrap() on Cyrix 486-class CPU. The bluetrap()
* set the magic number to tra_by_wrmsr.
*/
setidt(6, bluetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
wrmsr(0x1002, 0x03000000LL); /* Fault on Cyrix 486-class CPU. */
if (trap_by_wrmsr == 0xa8c1d)
return 0; /* Cyrix CPU sets the magic number. */
return 1; /* IBM Blue Lightnig CPU */
}
/*
* identifycyrix() set lower 16 bits of cyrix_did as follows:
*
* F E D C B A 9 8 7 6 5 4 3 2 1 0
* +-------+-------+---------------+
* | SID | RID | Device ID |
* | (DIR 1) | (DIR 0) |
* +-------+-------+---------------+
*/
static void
identifycyrix(void)
{
u_long eflags;
int ccr2_test = 0, dir_test = 0;
u_char ccr2, ccr3;
eflags = read_eflags();
disable_intr();
ccr2 = read_cyrix_reg(CCR2);
write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
read_cyrix_reg(CCR2);
if (read_cyrix_reg(CCR2) != ccr2)
ccr2_test = 1;
write_cyrix_reg(CCR2, ccr2);
ccr3 = read_cyrix_reg(CCR3);
write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
read_cyrix_reg(CCR3);
if (read_cyrix_reg(CCR3) != ccr3)
dir_test = 1; /* CPU supports DIRs. */
write_cyrix_reg(CCR3, ccr3);
if (dir_test) {
/* Device ID registers are available. */
cyrix_did = read_cyrix_reg(DIR1) << 8;
cyrix_did += read_cyrix_reg(DIR0);
} else if (ccr2_test)
cyrix_did = 0x0010; /* 486S A-step */
else
cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
write_eflags(eflags);
}
/*
* Final stage of CPU identification. -- Should I check TI?
*/
void
finishidentcpu(void)
{
if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
if (cpu == CPU_486) {
/*
* These conditions are equivalent to:
* - CPU does not support cpuid instruction.
* - Cyrix/IBM CPU is detected.
*/
if (identblue()) {
strcpy(cpu_vendor, "IBM");
cpu = CPU_BLUE;
return;
}
}
identifycyrix();
/*
* This routine contains a trick.
* Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
*/
switch (cyrix_did & 0x00f0) {
case 0x00:
case 0x10:
case 0xf0:
cpu = CPU_486DLC;
break;
case 0x20:
if ((cyrix_did & 0x00f0) < 8)
cpu = CPU_M1;
else
cpu = CPU_M1SC;
break;
case 0x30:
cpu = CPU_M1;
break;
case 0x40:
cpu = CPU_M1SC;
break;
default:
/* M2 and later CPUs are treated as M2. */
cpu = CPU_M2;
break;
}
}
}
/*
* This routine is called specifically to set up cpu_class before
* startrtclock() uses it. Probably this should be rearranged so that
@ -287,5 +569,6 @@ identifycpu(void)
void
earlysetcpuclass(void)
{
cpu_class = i386_cpus[cpu].cpu_class;
}

173
sys/i386/i386/locore.s
View file

@ -34,7 +34,7 @@
* SUCH DAMAGE.
*
* from: @(#)locore.s 7.3 (Berkeley) 5/13/91
* $Id$
* $Id: locore.s,v 1.81 1997/02/22 09:32:22 peter Exp $
*
* originally from: locore.s, by William F. Jolitz
*
@ -192,6 +192,21 @@ _bdb_exists: .long 0
*/
NON_GPROF_ENTRY(btext)
#ifdef PC98
jmp 1f
.globl _pc98_system_parameter
.org 0x400
_pc98_system_parameter:
.space 0x240 /* BIOS parameter block */
1:
/* save SYSTEM PARAMETER for resume (NS/T or other) */
movl $0xa1000,%esi
movl $0x100000,%edi
movl $0x0630,%ecx
cld
rep
movsb
#else /* IBM-PC */
#ifdef BDE_DEBUGGER
#ifdef BIOS_STEALS_3K
cmpl $0x0375c339,0x95504
@ -205,6 +220,7 @@ NON_GPROF_ENTRY(btext)
/* Tell the bios to warmboot next time */
movw $0x1234,0x472
#endif /* PC98 */
/* Set up a real frame in case the double return in newboot is executed. */
pushl %ebp
@ -232,6 +248,28 @@ NON_GPROF_ENTRY(btext)
*/
movl $R(tmpstk),%esp
#ifdef PC98
testb $0x02,0x100620 /* pc98_machine_type & M_EPSON_PC98 */
jz 3f
cmpb $0x0b,0x100624 /* epson_machine_id <= 0x0b */
ja 3f
/* count up memory */
movl $0x100000,%eax /* next, talley remaining memory */
movl $0xFFF-0x100,%ecx
1: movl 0(%eax),%ebx /* save location to check */
movl $0xa55a5aa5,0(%eax) /* write test pattern */
cmpl $0xa55a5aa5,0(%eax) /* does not check yet for rollover */
jne 2f
movl %ebx,0(%eax) /* restore memory */
addl $PAGE_SIZE,%eax
loop 1b
2: subl $0x100000,%eax
shrl $17,%eax
movb %al,0x100401
3:
#endif
call identify_cpu
/* clear bss */
@ -326,7 +364,7 @@ begin:
addl $(13*4),%esp /* back to a frame we can return with */
/*
* now we've run main() and determined what cpu-type we are, we can
* Now we've run main() and determined what cpu-type we are, we can
* enable write protection and alignment checking on i486 cpus and
* above.
*/
@ -524,7 +562,11 @@ olddiskboot:
movl %eax,R(_bootdev)
#if defined(USERCONFIG_BOOT) && defined(USERCONFIG)
#ifdef PC98
movl $0x90200, %esi
#else
movl $0x10200, %esi
#endif
movl $R(_userconfig_from_boot),%edi
movl $512,%ecx
cld
@ -557,11 +599,29 @@ identify_cpu:
popfl
testl %eax,%eax
jnz 1f
jnz try486
/* NexGen CPU does not have aligment check flag. */
pushfl
movl $0x5555, %eax
xorl %edx, %edx
movl $2, %ecx
clc
divl %ecx
jz trynexgen
popfl
movl $CPU_386,R(_cpu)
jmp 3f
1: /* Try to toggle identification flag; does not exist on early 486s. */
trynexgen:
movl $CPU_NX586,R(_cpu)
movl $0x4778654e,R(_cpu_vendor) # store vendor string
movl $0x72446e65,R(_cpu_vendor+4)
movl $0x6e657669,R(_cpu_vendor+8)
movl $0,R(_cpu_vendor+12)
jmp 3f
try486: /* Try to toggle identification flag; does not exist on early 486s. */
pushfl
popl %eax
movl %eax,%ecx
@ -576,89 +636,40 @@ identify_cpu:
popfl
testl %eax,%eax
jnz 1f
jnz trycpuid
movl $CPU_486,R(_cpu)
/* check for Cyrix 486DLC -- based on check routine */
/* documented in "Cx486SLC/e SMM Programmer's Guide" */
xorw %dx,%dx
cmpw %dx,%dx # set flags to known state
pushfw
popw %cx # store flags in ecx
movw $0xffff,%ax
movw $0x0004,%bx
divw %bx
pushfw
popw %ax
andw $0x08d5,%ax # mask off important bits
andw $0x08d5,%cx
cmpw %ax,%cx
/*
* Check Cyrix CPU
* Cyrix CPUs do not change the undefined flags following
* execution of the divide instruction which divides 5 by 2.
*
* Note: CPUID is enabled on M2, so it passes another way.
*/
pushfl
movl $0x5555, %eax
xorl %edx, %edx
movl $2, %ecx
clc
divl %ecx
jnc trycyrix
popfl
jmp 3f /* You may use Intel CPU. */
jnz 3f # if flags changed, Intel chip
movl $CPU_486DLC,R(_cpu) # set CPU value for Cyrix
trycyrix:
popfl
/*
* IBM Bluelighting CPU also doesn't change the undefined flags.
* Because IBM doesn't disclose the information for Bluelighting
* CPU, we couldn't distinguish it from Cyrix's (including IBM
* brand of Cyrix CPUs).
*/
movl $0x69727943,R(_cpu_vendor) # store vendor string
movw $0x0078,R(_cpu_vendor+4)
#ifndef CYRIX_CACHE_WORKS
/* Disable caching of the ISA hole only. */
invd
movb $CCR0,%al # Configuration Register index (CCR0)
outb %al,$0x22
inb $0x23,%al
orb $(CCR0_NC1|CCR0_BARB),%al
movb %al,%ah
movb $CCR0,%al
outb %al,$0x22
movb %ah,%al
outb %al,$0x23
invd
#else /* CYRIX_CACHE_WORKS */
/* Set cache parameters */
invd # Start with guaranteed clean cache
movb $CCR0,%al # Configuration Register index (CCR0)
outb %al,$0x22
inb $0x23,%al
andb $~CCR0_NC0,%al
#ifndef CYRIX_CACHE_REALLY_WORKS
orb $(CCR0_NC1|CCR0_BARB),%al
#else /* CYRIX_CACHE_REALLY_WORKS */
orb $CCR0_NC1,%al
#endif /* !CYRIX_CACHE_REALLY_WORKS */
movb %al,%ah
movb $CCR0,%al
outb %al,$0x22
movb %ah,%al
outb %al,$0x23
/* clear non-cacheable region 1 */
movb $(NCR1+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* clear non-cacheable region 2 */
movb $(NCR2+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* clear non-cacheable region 3 */
movb $(NCR3+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* clear non-cacheable region 4 */
movb $(NCR4+2),%al
outb %al,$0x22
movb $NCR_SIZE_0K,%al
outb %al,$0x23
/* enable caching in CR0 */
movl %cr0,%eax
andl $~(CR0_CD|CR0_NW),%eax
movl %eax,%cr0
invd
#endif /* !CYRIX_CACHE_WORKS */
movl $0x736e4978,R(_cpu_vendor+4)
movl $0x64616574,R(_cpu_vendor+8)
jmp 3f
1: /* Use the `cpuid' instruction. */
trycpuid: /* Use the `cpuid' instruction. */
xorl %eax,%eax
.byte 0x0f,0xa2 # cpuid 0
movl %eax,R(_cpu_high) # highest capability

14
sys/i386/i386/machdep.c
View file

@ -35,7 +35,7 @@
* SUCH DAMAGE.
*
* from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
* $Id: machdep.c,v 1.228 1997/02/22 09:32:26 peter Exp $
* $Id: machdep.c,v 1.229 1997/02/24 00:37:43 alex Exp $
*/
#include "npx.h"
@ -122,8 +122,11 @@ extern int ptrace_single_step __P((struct proc *p));
extern int ptrace_write_u __P((struct proc *p, vm_offset_t off, int data));
extern void dblfault_handler __P((void));
extern void identifycpu(void); /* XXX header file */
extern void printcpuinfo(void); /* XXX header file */
extern void earlysetcpuclass(void); /* same header file */
extern void finishidentcpu(void);
extern void panicifcpuunsupported(void);
extern void initializecpu(void);
static void cpu_startup __P((void *));
SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
@ -208,7 +211,8 @@ cpu_startup(dummy)
printf(version);
earlysetcpuclass();
startrtclock();
identifycpu();
printcpuinfo();
panicifcpuunsupported();
#ifdef PERFMON
perfmon_init();
#endif
@ -1059,6 +1063,10 @@ init386(first)
Debugger("Boot flags requested debugger");
#endif
finishidentcpu(); /* Final stage of CPU initialization */
setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
initializecpu(); /* Initialize CPU registers */
/* Use BIOS values stored in RTC CMOS RAM, since probing
* breaks certain 386 AT relics.
*/

16
sys/i386/include/cpufunc.h
View file

@ -30,7 +30,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
* $Id: cpufunc.h,v 1.61 1997/02/22 09:34:08 peter Exp $
*/
/*
@ -195,6 +195,12 @@ insl(u_int port, void *addr, size_t cnt)
: "di", "cx", "memory");
}
static __inline void
invd(void)
{
__asm __volatile("invd");
}
static __inline void
invlpg(u_int addr)
{
@ -338,6 +344,12 @@ setbits(volatile unsigned *addr, u_int bits)
__asm __volatile("orl %1,%0" : "=m" (*addr) : "ir" (bits));
}
static __inline void
wbinvd(void)
{
__asm __volatile("wbinvd");
}
static __inline void
write_eflags(u_long ef)
{
@ -360,6 +372,7 @@ u_long inl __P((u_int port));
void insb __P((u_int port, void *addr, size_t cnt));
void insl __P((u_int port, void *addr, size_t cnt));
void insw __P((u_int port, void *addr, size_t cnt));
void invd __P((void));
void invlpg __P((u_int addr));
void invltlb __P((void));
u_short inw __P((u_int port));
@ -376,6 +389,7 @@ quad_t rdpmc __P((u_int pmc));
quad_t rdtsc __P((void));
u_long read_eflags __P((void));
void setbits __P((volatile unsigned *addr, u_int bits));
void wbinvd __P((void));
void write_eflags __P((u_long ef));
void wrmsr __P((u_int msr, quad_t newval));

8
sys/i386/include/cputypes.h
View file

@ -24,7 +24,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id$
* $Id: cputypes.h,v 1.7 1997/02/22 09:34:14 peter Exp $
*/
#ifndef _MACHINE_CPUTYPES_H_
@ -52,5 +52,9 @@
#define CPU_586 5 /* Intel P.....m (I hate lawyers; it's TM) */
#define CPU_486DLC 6 /* Cyrix 486DLC */
#define CPU_686 7 /* Pentium Pro */
#define CPU_M1SC 8 /* Cyrix M1sc (aka 5x86) */
#define CPU_M1 9 /* Cyrix M1 (aka 6x86) */
#define CPU_BLUE 10 /* IBM BlueLighting CPU */
#define CPU_M2 11 /* Cyrix M2 (aka enhanced 6x86 with MMX */
#define CPU_NX586 12 /* NexGen (now AMD) 586 */
#endif /* _MACHINE_CPUTYPES_H_ */

8
sys/i386/include/md_var.h
View file

@ -26,7 +26,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
* $Id: md_var.h,v 1.12 1997/02/22 09:34:49 peter Exp $
*/
#ifndef _MACHINE_MD_VAR_H_
@ -41,6 +41,7 @@ extern u_int atdevbase; /* offset in virtual memory of ISA io mem */
extern u_long cpu_feature;
extern u_long cpu_high;
extern u_long cpu_id;
extern u_long cyrix_did;
extern char cpu_vendor[];
extern char etext[];
extern char kstack[];
@ -72,4 +73,9 @@ void userconfig __P((void));
void vm_bounce_init __P((void));
int vm_page_zero_idle __P((void));
#ifdef PC98
extern int need_pre_dma_flush;
extern int need_post_dma_flush;
#endif
#endif /* !_MACHINE_MD_VAR_H_ */

212
sys/i386/include/specialreg.h
View file

@ -31,7 +31,7 @@
* SUCH DAMAGE.
*
* from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
* $Id$
* $Id: specialreg.h,v 1.12 1997/02/22 09:35:15 peter Exp $
*/
#ifndef _MACHINE_SPECIALREG_H_
@ -54,11 +54,12 @@
/*
* Bits in 486 special registers:
*/
#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
#define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */
#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
#define CR0_NW 0x20000000 /* Not Write-through */
#define CR0_CD 0x40000000 /* Cache Disable */
#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
#define CR0_WP 0x00010000 /* Write Protect (honor page protect in
all modes) */
#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
#define CR0_NW 0x20000000 /* Not Write-through */
#define CR0_CD 0x40000000 /* Cache Disable */
/*
* Bits in PPro special registers
@ -94,26 +95,81 @@
#define CPUID_CMOV 0x8000
/*
* Cyrix 486 DLC special registers, accessible as IO ports.
* Cyrix configuration registers, accessible as IO ports.
*/
#define CCR0 0xc0 /* configuration control register 0 */
#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is
non-cacheable */
#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
#define CCR0_A20M 0x04 /* enables A20M# input pin */
#define CCR0_KEN 0x08 /* enables KEN# input pin */
#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
#define CCR0_BARB 0x20 /* flushes internal cache when entering hold
state */
#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
#define CCR0 0xc0 /* Configuration control register 0 */
#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
non-cacheable */
#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
#define CCR0_A20M 0x04 /* Enables A20M# input pin */
#define CCR0_KEN 0x08 /* Enables KEN# input pin */
#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
state */
#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
assoc */
#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
#define CCR1 0xc1 /* configuration control register 1 */
#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
/* the remaining 7 bits of this register are reserved */
#define CCR1 0xc1 /* Configuration control register 1 */
#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
#define CCR1_SMI 0x02 /* Enables SMM pins */
#define CCR1_SMAC 0x04 /* System management memory access */
#define CCR1_MMAC 0x08 /* Main memory access */
#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
#define CCR1_SM3 0x80 /* SMM address space address region 3 */
#define CCR2 0xc2
#define CCR2_WB 0x02 /* Enables WB cache interface pins */
#define CCR2_SADS 0x02 /* Slow ADS */
#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
#define CCR2_WT1 0x10 /* WT region 1 */
#define CCR2_WPR1 0x10 /* Write-protect region 1 */
#define CCR2_BARB 0x20 /* Flushes write-back cache when entering
hold state. */
#define CCR2_BWRT 0x40 /* Enables burst write cycles */
#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
#define CCR3 0xc3
#define CCR3_SMILOCK 0x01 /* SMM register lock */
#define CCR3_NMI 0x02 /* Enables NMI during SMM */
#define CCR3_LINBRST 0x04 /* Linear address burst cycles */
#define CCR3_SMMMODE 0x08 /* SMM Mode */
#define CCR3_MAPEN0 0x10 /* Enables Map0 */
#define CCR3_MAPEN1 0x20 /* Enables Map1 */
#define CCR3_MAPEN2 0x40 /* Enables Map2 */
#define CCR3_MAPEN3 0x80 /* Enables Map3 */
#define CCR4 0xe8
#define CCR4_IOMASK 0x07
#define CCR4_MEM 0x08 /* Enables momory bypassing */
#define CCR4_DTE 0x10 /* Enables directory table entry cache */
#define CCR4_FASTFPE 0x20 /* Fast FPU exception */
#define CCR4_CPUID 0x80 /* Enables CPUID instruction */
#define CCR5 0xe9
#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
#define CCR5_LBR1 0x10 /* Local bus region 1 */
#define CCR5_ARREN 0x20 /* Enables ARR region */
/* Performance Control Register (5x86 only). */
#define PCR0 0x20
#define PCR0_RSTK 0x01 /* Enables return stack */
#define PCR0_BTB 0x02 /* Enables branch target buffer */
#define PCR0_LOOP 0x04 /* Enables loop */
#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
serialize pipe. */
#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
#define PCR0_BTBRT 0x40 /* Enables BTB test register. */
#define PCR0_LSSER 0x80 /* Disable reorder */
/* Device Identification Registers */
#define DIR0 0xfe
#define DIR1 0xff
/*
* the following four 3-byte registers control the non-cacheable regions.
* The following four 3-byte registers control the non-cacheable regions.
* These registers must be written as three separate bytes.
*
* NCRx+0: A31-A24 of starting address
@ -123,26 +179,98 @@
* The non-cacheable region's starting address must be aligned to the
* size indicated by the NCR_SIZE_xx field.
*/
#define NCR1 0xc4
#define NCR2 0xc7
#define NCR3 0xca
#define NCR4 0xcd
#define NCR1 0xc4
#define NCR2 0xc7
#define NCR3 0xca
#define NCR4 0xcd
#define NCR_SIZE_0K 0
#define NCR_SIZE_4K 1
#define NCR_SIZE_8K 2
#define NCR_SIZE_16K 3
#define NCR_SIZE_32K 4
#define NCR_SIZE_64K 5
#define NCR_SIZE_128K 6
#define NCR_SIZE_256K 7
#define NCR_SIZE_512K 8
#define NCR_SIZE_1M 9
#define NCR_SIZE_2M 10
#define NCR_SIZE_4M 11
#define NCR_SIZE_8M 12
#define NCR_SIZE_16M 13
#define NCR_SIZE_32M 14
#define NCR_SIZE_4G 15
#define NCR_SIZE_0K 0
#define NCR_SIZE_4K 1
#define NCR_SIZE_8K 2
#define NCR_SIZE_16K 3
#define NCR_SIZE_32K 4
#define NCR_SIZE_64K 5
#define NCR_SIZE_128K 6
#define NCR_SIZE_256K 7
#define NCR_SIZE_512K 8
#define NCR_SIZE_1M 9
#define NCR_SIZE_2M 10
#define NCR_SIZE_4M 11
#define NCR_SIZE_8M 12
#define NCR_SIZE_16M 13
#define NCR_SIZE_32M 14
#define NCR_SIZE_4G 15
/*
* The address region registers are used to specify the location and
* size for the eight address regions.
*
* ARRx + 0: A31-A24 of start address
* ARRx + 1: A23-A16 of start address
* ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
*/
#define ARR0 0xc4
#define ARR1 0xc7
#define ARR2 0xca
#define ARR3 0xcd
#define ARR4 0xd0
#define ARR5 0xd3
#define ARR6 0xd6
#define ARR7 0xd9
#define ARR_SIZE_0K 0
#define ARR_SIZE_4K 1
#define ARR_SIZE_8K 2
#define ARR_SIZE_16K 3
#define ARR_SIZE_32K 4
#define ARR_SIZE_64K 5
#define ARR_SIZE_128K 6
#define ARR_SIZE_256K 7
#define ARR_SIZE_512K 8
#define ARR_SIZE_1M 9
#define ARR_SIZE_2M 10
#define ARR_SIZE_4M 11
#define ARR_SIZE_8M 12
#define ARR_SIZE_16M 13
#define ARR_SIZE_32M 14
#define ARR_SIZE_4G 15
/*
* The region control registers specify the attributes associated with
* the ARRx addres regions.
*/
#define RCR0 0xdc
#define RCR1 0xdd
#define RCR2 0xde
#define RCR3 0xdf
#define RCR4 0xe0
#define RCR5 0xe1
#define RCR6 0xe2
#define RCR7 0xe3
#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
#define RCR_RCE 0x01 /* Enables caching for ARR7. */
#define RCR_WWO 0x02 /* Weak write ordering. */
#define RCR_WL 0x04 /* Weak locking. */
#define RCR_WG 0x08 /* Write gathering. */
#define RCR_WT 0x10 /* Write-through. */
#define RCR_NLB 0x20 /* LBA# pin is not asserted. */
#ifndef LOCORE
static __inline u_char
read_cyrix_reg(u_char reg)
{
outb(0x22, reg);
return inb(0x23);
}
static __inline void
write_cyrix_reg(u_char reg, u_char data)
{
outb(0x22, reg);
outb(0x23, data);
}
#endif
#endif /* !_MACHINE_SPECIALREG_H_ */

10
sys/i386/isa/bs/bshw_dma.c
View file

@ -200,9 +200,8 @@ bshw_dmastart(bsc)
*/
/* set dma channel mode, and reset address ff */
#ifdef __FreeBSD__
#ifdef CYRIX_5X86
asm("wbinvd");
#endif
if (need_pre_dma_flush)
wbinvd();
#else /* NetBSD/pc98 */
if (cpuspec->cpuspec_cache_flush_before)
(*cpuspec->cpuspec_cache_flush_before)();
@ -247,9 +246,8 @@ bshw_dmadone(bsc)
(*bsc->sc_hw->dma_stop)(bsc);
#ifdef __FreeBSD__
#if defined(CYRIX_486DLC) || defined(IBM_486SLC)
asm(".byte 0x0f, 0x08");
#endif
if (need_post_dma_flush)
invd();
#else
if (cpuspec->cpuspec_cache_flush_after)
(*cpuspec->cpuspec_cache_flush_after)();

1
sys/i386/isa/bs/bsif.h
View file

@ -101,6 +101,7 @@
#include <vm/vm_kern.h>
#include <machine/clock.h>
#include <machine/cpu.h>
#include <machine/md_var.h>
#include <machine/vmparam.h>
#include <vm/pmap.h>
#include <sys/proc.h>

8
sys/pc98/conf/Makefile.pc98
View file

@ -3,7 +3,7 @@
# Makefile.i386 -- with config changes.
# Copyright 1990 W. Jolitz
# from: @(#)Makefile.i386 7.1 5/10/91
# $Id$
# $Id: Makefile.pc98,v 1.11 1997/02/22 09:43:21 peter Exp $
#
# Makefile for FreeBSD
#
@ -58,7 +58,7 @@ DRIVER_S= ${CC} -c -x assembler-with-cpp -DLOCORE ${COPTS} $<
PROFILE_C= ${CC} -c ${CFLAGS} ${PARAM} $<
SYSTEM_CFILES= ioconf.c param.c vnode_if.c config.c
SYSTEM_SFILES= ${PC98}/i386/locore.s
SYSTEM_SFILES= ${I386}/i386/locore.s
SYSTEM_OBJS= locore.o vnode_if.o ${OBJS} ioconf.o param.o config.o
SYSTEM_DEP= Makefile symbols.exclude symbols.sort ${SYSTEM_OBJS}
SYSTEM_LD_HEAD= @echo loading $@; rm -f $@
@ -89,7 +89,7 @@ clean:
#lint: /tmp param.c
# @lint -hbxn -DGENERIC -Dvolatile= ${COPTS} ${PARAM} \
# ${PC98}/i386/Locore.c ${CFILES} ioconf.c param.c | \
# ${I386}/i386/Locore.c ${CFILES} ioconf.c param.c | \
# grep -v 'struct/union .* never defined' | \
# grep -v 'possible pointer alignment problem'
@ -101,7 +101,7 @@ symbols.sort: ${I386}/i386/symbols.raw
grep -v '^#' ${I386}/i386/symbols.raw \
| sed 's/^ //' | sort -u > symbols.sort
locore.o: ${PC98}/i386/locore.s assym.s
locore.o: ${I386}/i386/locore.s assym.s
${NORMAL_S}
# everything potentially depends on the Makefile since everything potentially

3
sys/pc98/conf/files.pc98
View file

@ -3,7 +3,7 @@
#
# modified for PC-9801
#
# $Id: files.pc98,v 1.16 1997/02/22 09:43:22 peter Exp $
# $Id: files.pc98,v 1.17 1997/03/19 16:14:25 kato Exp $
#
aic7xxx_asm optional ahc device-driver \
dependency "$S/dev/aic7xxx/*.[chyl]" \
@ -49,6 +49,7 @@ i386/i386/i386-gdbstub.c optional ddb
i386/i386/exception.s standard
i386/i386/identcpu.c standard
i386/i386/in_cksum.c optional inet
i386/i386/initcpu.c standard
# locore.s needs to be handled in Makefile to put it first. Otherwise it's
# now normal.
# i386/i386/locore.s standard

21
sys/pc98/conf/options.pc98
View file

@ -1,4 +1,4 @@
# $Id: options.pc98,v 1.17 1997/03/01 11:06:41 kato Exp $
# $Id: options.pc98,v 1.18 1997/03/13 17:04:23 kato Exp $
BOUNCEPAGES opt_bounce.h
USER_LDT
MATH_EMULATE opt_math_emulate.h
@ -37,10 +37,21 @@ CLK_CALIBRATION_LOOP opt_clock.h
CLK_USE_I8254_CALIBRATION opt_clock.h
CLK_USE_I586_CALIBRATION opt_clock.h
I386_CPU opt_cpu.h
I486_CPU opt_cpu.h
I586_CPU opt_cpu.h
I686_CPU opt_cpu.h
CPU_BTB_EN opt_cpu.h
CPU_DISABLE_5X86_LSSER opt_cpu.h
CPU_FASTER_5X86_FPU opt_cpu.h
CPU_I486_ON_386 opt_cpu.h
CPU_IORT opt_cpu.h
CPU_LOOP_EN opt_cpu.h
CPU_RSTK_EN opt_cpu.h
CPU_SUSP_HLT opt_cpu.h
CPU_UPGRADE_HW_CACHE opt_cpu.h
CYRIX_CACHE_WORKS opt_cpu.h
CYRIX_CACHE_REALLY_WORKS opt_cpu.h
I386_CPU opt_cpu.h
I486_CPU opt_cpu.h
I586_CPU opt_cpu.h
I686_CPU opt_cpu.h
SC_SPLASH_SCREEN opt_syscons.h
MAXCONS opt_syscons.h

1084
sys/pc98/i386/locore.s
View file

File diff suppressed because it is too large Load diff

20
sys/pc98/i386/machdep.c
View file

@ -35,7 +35,7 @@
* SUCH DAMAGE.
*
* from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
* $Id: machdep.c,v 1.28 1997/02/22 09:43:27 peter Exp $
* $Id: machdep.c,v 1.29 1997/02/25 16:36:48 kato Exp $
*/
#include "npx.h"
@ -126,12 +126,19 @@ extern int ptrace_single_step __P((struct proc *p));
extern int ptrace_write_u __P((struct proc *p, vm_offset_t off, int data));
extern void dblfault_handler __P((void));
extern void identifycpu(void); /* XXX header file */
extern void printcpuinfo(void); /* XXX header file */
extern void earlysetcpuclass(void); /* same header file */
extern void finishidentcpu(void);
extern void panicifcpuunsupported(void);
extern void initializecpu(void);
static void cpu_startup __P((void *));
SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
#ifdef PC98
int need_pre_dma_flush; /* If 1, use wbinvd befor DMA transfer. */
int need_post_dma_flush; /* If 1, use invd after DMA transfer. */
#endif
#ifdef BOUNCE_BUFFERS
extern char *bouncememory;
@ -215,7 +222,8 @@ cpu_startup(dummy)
printf(version);
earlysetcpuclass();
startrtclock();
identifycpu();
printcpuinfo();
panicifcpuunsupported();
#ifdef PERFMON
perfmon_init();
#endif
@ -1041,7 +1049,7 @@ init386(first)
setidt(11, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
setidt(12, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
#if defined(CYRIX_486DLC) || defined(CYRIX_5X86)
#ifdef CPU_BUGGY_CYRIX
setidt(14, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
#else
setidt(14, &IDTVEC(page), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
@ -1077,6 +1085,10 @@ init386(first)
Debugger("Boot flags requested debugger");
#endif
finishidentcpu(); /* Final stage of CPU initialization */
setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
initializecpu(); /* Initialize CPU registers */
#ifdef PC98
pc98_getmemsize();
biosbasemem = 640; /* 640KB */

22
sys/pc98/i386/trap.c
View file

@ -35,7 +35,7 @@
* SUCH DAMAGE.
*
* from: @(#)trap.c 7.4 (Berkeley) 5/13/91
* $Id$
* $Id: trap.c,v 1.13 1997/02/22 09:43:28 peter Exp $
*/
/*
@ -91,7 +91,7 @@ extern void trap __P((struct trapframe frame));
extern int trapwrite __P((unsigned addr));
extern void syscall __P((struct trapframe frame));
#if defined(CYRIX_486DLC) || defined(CYRIX_5X86)
#ifdef CPU_BUGGY_CYRIX
static int trap_pfault __P((struct trapframe *, int, vm_offset_t));
#else
static int trap_pfault __P((struct trapframe *, int));
@ -192,14 +192,14 @@ trap(frame)
#ifdef DEBUG
u_long eva;
#endif
#if defined(CYRIX_486DLC) || defined(CYRIX_5X86)
#ifdef CPU_BUGGY_CYRIX
vm_offset_t va;
#endif
type = frame.tf_trapno;
code = frame.tf_err;
#if defined(CYRIX_486DLC) || defined(CYRIX_5X86)
#ifdef CPU_BUGGY_CYRIX
/* XXX:
* CYRIX 486 CPU FIX.
* If you use cyrix cpu, you often encouter strange signal 11's?
@ -210,7 +210,7 @@ trap(frame)
va = (vm_offset_t)(rcr2());
if( type == T_PAGEFLT && ( frame.tf_eflags & PSL_I ) )
asm("sti");
#endif /* CYRIX_486DLC || CYRIX_5X86 */
#endif /* CPU_BUGGY_CYRIX */
if (ISPL(frame.tf_cs) == SEL_UPL) {
/* user trap */
@ -256,7 +256,7 @@ trap(frame)
break;
case T_PAGEFLT: /* page fault */
#if defined(CYRIX_486DLC) || defined(CYRIX_5X86)
#ifdef CPU_BUGGY_CYRIX
i = trap_pfault(&frame, TRUE, va);
#else
i = trap_pfault(&frame, TRUE);
@ -332,7 +332,7 @@ trap(frame)
switch (type) {
case T_PAGEFLT: /* page fault */
#if defined(CYRIX_486DLC) || defined(CYRIX_5X86)
#ifdef CPU_BUGGY_CYRIX
(void) trap_pfault(&frame, FALSE, va);
#else
(void) trap_pfault(&frame, FALSE);
@ -495,7 +495,7 @@ out:
* debugging code.
*/
static int
#if defined(CYRIX_486DLC) || defined(CYRIX_5X86)
#ifdef CPU_BUGGY_CYRIX
trap_pfault(frame, usermode,faultva)
struct trapframe *frame;
int usermode;
@ -519,7 +519,7 @@ trap_pfault(frame, usermode)
else
ftype = VM_PROT_READ;
#if defined(CYRIX_486DLC) || defined(CYRIX_5X86)
#ifdef CPU_BUGGY_CYRIX
eva = faultva;
#else
eva = rcr2();
@ -606,7 +606,7 @@ nogo:
#endif
int
#if defined(CYRIX_486DLC) || defined(CYRIX_5X86)
#ifdef CPU_BUGGY_CYRIX
trap_pfault(frame, usermode,faultva)
struct trapframe *frame;
int usermode;
@ -625,7 +625,7 @@ trap_pfault(frame, usermode)
int eva;
struct proc *p = curproc;
#if defined(CYRIX_486DLC) || defined(CYRIX_5X86)
#ifdef CPU_BUGGY_CYRIX
eva = faultva;
#else
eva = rcr2();

20
sys/pc98/pc98/machdep.c
View file

@ -35,7 +35,7 @@
* SUCH DAMAGE.
*
* from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
* $Id: machdep.c,v 1.28 1997/02/22 09:43:27 peter Exp $
* $Id: machdep.c,v 1.29 1997/02/25 16:36:48 kato Exp $
*/
#include "npx.h"
@ -126,12 +126,19 @@ extern int ptrace_single_step __P((struct proc *p));
extern int ptrace_write_u __P((struct proc *p, vm_offset_t off, int data));
extern void dblfault_handler __P((void));
extern void identifycpu(void); /* XXX header file */
extern void printcpuinfo(void); /* XXX header file */
extern void earlysetcpuclass(void); /* same header file */
extern void finishidentcpu(void);
extern void panicifcpuunsupported(void);
extern void initializecpu(void);
static void cpu_startup __P((void *));
SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
#ifdef PC98
int need_pre_dma_flush; /* If 1, use wbinvd befor DMA transfer. */
int need_post_dma_flush; /* If 1, use invd after DMA transfer. */
#endif
#ifdef BOUNCE_BUFFERS
extern char *bouncememory;
@ -215,7 +222,8 @@ cpu_startup(dummy)
printf(version);
earlysetcpuclass();
startrtclock();
identifycpu();
printcpuinfo();
panicifcpuunsupported();
#ifdef PERFMON
perfmon_init();
#endif
@ -1041,7 +1049,7 @@ init386(first)
setidt(11, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
setidt(12, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
#if defined(CYRIX_486DLC) || defined(CYRIX_5X86)
#ifdef CPU_BUGGY_CYRIX
setidt(14, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
#else
setidt(14, &IDTVEC(page), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
@ -1077,6 +1085,10 @@ init386(first)
Debugger("Boot flags requested debugger");
#endif
finishidentcpu(); /* Final stage of CPU initialization */
setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
initializecpu(); /* Initialize CPU registers */
#ifdef PC98
pc98_getmemsize();
biosbasemem = 640; /* 640KB */

14
sys/pc98/pc98/pc98.c
View file

@ -34,7 +34,7 @@
* SUCH DAMAGE.
*
* from: @(#)isa.c 7.2 (Berkeley) 5/13/91
* $Id$
* $Id: pc98.c,v 1.18 1997/02/22 09:43:42 peter Exp $
*/
/*
@ -67,6 +67,7 @@
#include <vm/pmap.h>
#include <i386/isa/isa_device.h>
#ifdef PC98
#include <machine/cpufunc.h>
#include <pc98/pc98/pc98.h>
#include <pc98/pc98/pc98_machdep.h>
#include <pc98/pc98/epsonio.h>
@ -734,9 +735,9 @@ void isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan)
/* translate to physical */
phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr);
#ifdef CYRIX_5X86
asm("wbinvd"); /* wbinvd (WB cache flush) */
#endif
if (need_pre_dma_flush)
wbinvd(); /* wbinvd (WB cache flush) */
#ifndef PC98
if ((chan & 4) == 0) {
@ -814,12 +815,11 @@ void isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan)
void isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
{
#if defined(CYRIX_486DLC) || defined(IBM_486SLC)
if (flags & B_READ) {
/* cache flush only after reading 92/12/9 by A.Kojima */
asm(" .byte 0x0f,0x08"); /* invd (cache flush) */
if (need_post_dma_flush)
invd();
}
#endif
#ifdef DIAGNOSTIC
if (chan & ~VALID_DMA_MASK)