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amdiommu: Fix device table segment base register offsets

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Segment base registers are at 8-byte intervals, while the register
write helper takes a byte-aligned offset.  This fixes
DEV_TAB_HARDWARE_ERROR events and associated peripheral I/O failures
on an Epyc-based system with 8-segment device tables.

Reviewed by:		kib
Differential Revision:	https://reviews.freebsd.org/D47752
This commit is contained in:
Jason A. Harmening 2024-11-25 17:24:41 -06:00
parent 501c4801ed
commit 5035db222e
1 changed files with 1 additions and 1 deletions
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2
sys/x86/iommu/amd_drv.c
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@ -277,7 +277,7 @@ amdiommu_create_dev_tbl(struct amdiommu_unit *sc)
pmap_qenter(seg_vaddr, &m, 1);
}
reg = i == 0 ? AMDIOMMU_DEVTAB_BASE : AMDIOMMU_DEVTAB_S1_BASE +
i - 1;
((i - 1) << 3);
amdiommu_write8(sc, reg, rval);
}