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x86: Probe the TSC frequency earlier
This lets us use the TSC to implement early DELAY, limiting the use of the sometimes-unreliable 8254 PIT. PR: 262155 Reviewed by: emaste Tested by: emaste, mike tancsa <mike@sentex.net>, Stefan Hegnauer <stefan.hegnauer@gmx.ch> MFC after: 1 month Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D34367
This commit is contained in:
Mark Johnston
parent
c3d830cf7c
commit
84369dd523
5 changed files with 94 additions and 61 deletions
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@ -169,6 +169,9 @@ extern u_int64_t hammer_time(u_int64_t, u_int64_t);
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static void cpu_startup(void *);
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SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
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/* Probe 8254 PIT and TSC. */
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static void native_clock_source_init(void);
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/* Preload data parse function */
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static caddr_t native_parse_preload_data(u_int64_t);
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@ -177,8 +180,8 @@ static void native_parse_memmap(caddr_t, vm_paddr_t *, int *);
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/* Default init_ops implementation. */
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struct init_ops init_ops = {
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.parse_preload_data = native_parse_preload_data,
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.early_clock_source_init = i8254_init,
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.parse_preload_data = native_parse_preload_data,
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.early_clock_source_init = native_clock_source_init,
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.early_delay = i8254_delay,
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.parse_memmap = native_parse_memmap,
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};
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@ -1160,6 +1163,13 @@ native_parse_preload_data(u_int64_t modulep)
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return (kmdp);
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}
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static void
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native_clock_source_init(void)
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{
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i8254_init();
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tsc_init();
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}
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static void
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amd64_kdb_init(void)
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{
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@ -188,6 +188,8 @@ struct kva_md_info kmi;
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static struct trapframe proc0_tf;
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struct pcpu __pcpu[MAXCPU];
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static void i386_clock_source_init(void);
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struct mtx icu_lock;
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struct mem_range_softc mem_range_softc;
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@ -198,10 +200,17 @@ extern struct sysentvec elf32_freebsd_sysvec;
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/* Default init_ops implementation. */
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struct init_ops init_ops = {
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.early_clock_source_init = i8254_init,
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.early_clock_source_init = i386_clock_source_init,
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.early_delay = i8254_delay,
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};
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static void
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i386_clock_source_init(void)
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{
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i8254_init();
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tsc_init();
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}
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static void
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cpu_startup(dummy)
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void *dummy;
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@ -28,6 +28,7 @@ void i8254_init(void);
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void i8254_delay(int);
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void clock_init(void);
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void lapic_calibrate(void);
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void tsc_init(void);
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void tsc_calibrate(void);
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/*
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@ -35,7 +36,7 @@ void tsc_calibrate(void);
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*/
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void startrtclock(void);
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void init_TSC(void);
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void start_TSC(void);
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void resume_TSC(void);
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#define HAS_TIMER_SPKR 1
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@ -398,10 +398,10 @@ i8254_init(void)
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}
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void
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startrtclock()
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startrtclock(void)
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{
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init_TSC();
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start_TSC();
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}
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void
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@ -265,17 +265,42 @@ tsc_freq_8254(uint64_t *res)
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static void
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probe_tsc_freq(void)
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{
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if (cpu_power_ecx & CPUID_PERF_STAT) {
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/*
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* XXX Some emulators expose host CPUID without actual support
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* for these MSRs. We must test whether they really work.
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*/
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wrmsr(MSR_MPERF, 0);
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wrmsr(MSR_APERF, 0);
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DELAY(10);
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if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0)
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tsc_perf_stat = 1;
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#ifdef __i386__
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/* The TSC is known to be broken on certain CPUs. */
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switch (cpu_vendor_id) {
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case CPU_VENDOR_AMD:
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switch (cpu_id & 0xFF0) {
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case 0x500:
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/* K5 Model 0 */
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tsc_disabled = 1;
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return;
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}
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break;
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case CPU_VENDOR_CENTAUR:
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switch (cpu_id & 0xff0) {
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case 0x540:
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/*
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* http://www.centtech.com/c6_data_sheet.pdf
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*
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* I-12 RDTSC may return incoherent values in EDX:EAX
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* I-13 RDTSC hangs when certain event counters are used
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*/
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tsc_disabled = 1;
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return;
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}
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break;
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case CPU_VENDOR_NSC:
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switch (cpu_id & 0xff0) {
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case 0x540:
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if ((cpu_id & CPUID_STEPPING) == 0) {
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tsc_disabled = 1;
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return;
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}
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break;
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}
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break;
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}
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#endif
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switch (cpu_vendor_id) {
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case CPU_VENDOR_AMD:
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@ -315,15 +340,18 @@ probe_tsc_freq(void)
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break;
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}
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if (tsc_freq_cpuid_vm())
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return;
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if (vm_guest == VM_GUEST_VMWARE) {
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if (tsc_freq_cpuid_vm()) {
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if (bootverbose)
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printf(
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"Early TSC frequency %juHz derived from hypervisor CPUID\n",
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(uintmax_t)tsc_freq);
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} else if (vm_guest == VM_GUEST_VMWARE) {
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tsc_freq_vmware();
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return;
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}
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if (tsc_freq_cpuid(&tsc_freq)) {
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if (bootverbose)
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printf(
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"Early TSC frequency %juHz derived from VMWare hypercall\n",
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(uintmax_t)tsc_freq);
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} else if (tsc_freq_cpuid(&tsc_freq)) {
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/*
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* If possible, use the value obtained from CPUID as the initial
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* frequency. This will be refined later during boot but is
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@ -361,50 +389,26 @@ probe_tsc_freq(void)
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"Early TSC frequency %juHz calibrated from 8254 PIT\n",
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(uintmax_t)tsc_freq);
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}
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if (cpu_power_ecx & CPUID_PERF_STAT) {
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/*
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* XXX Some emulators expose host CPUID without actual support
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* for these MSRs. We must test whether they really work.
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*/
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wrmsr(MSR_MPERF, 0);
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wrmsr(MSR_APERF, 0);
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DELAY(10);
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if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0)
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tsc_perf_stat = 1;
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}
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}
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void
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init_TSC(void)
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start_TSC(void)
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{
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if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled)
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return;
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#ifdef __i386__
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/* The TSC is known to be broken on certain CPUs. */
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switch (cpu_vendor_id) {
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case CPU_VENDOR_AMD:
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switch (cpu_id & 0xFF0) {
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case 0x500:
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/* K5 Model 0 */
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return;
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}
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break;
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case CPU_VENDOR_CENTAUR:
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switch (cpu_id & 0xff0) {
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case 0x540:
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/*
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* http://www.centtech.com/c6_data_sheet.pdf
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*
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* I-12 RDTSC may return incoherent values in EDX:EAX
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* I-13 RDTSC hangs when certain event counters are used
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*/
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return;
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}
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break;
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case CPU_VENDOR_NSC:
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switch (cpu_id & 0xff0) {
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case 0x540:
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if ((cpu_id & CPUID_STEPPING) == 0)
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return;
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break;
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}
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break;
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}
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#endif
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probe_tsc_freq();
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/*
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* Inform CPU accounting about our boot-time clock rate. This will
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* be updated if someone loads a cpufreq driver after boot that
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@ -708,6 +712,15 @@ tsc_update_freq(uint64_t new_freq)
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new_freq >> (int)(intptr_t)tsc_timecounter.tc_priv);
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}
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void
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tsc_init(void)
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{
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if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled)
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return;
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probe_tsc_freq();
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}
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/*
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* Perform late calibration of the TSC frequency once ACPI-based timecounters
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* are available. At this point timehands are not set up, so we read the
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