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Print missing ID_AA64PFR{0,1}_EL1 register fields.
MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D23213
This commit is contained in:
Mark Johnston
parent
32a1f92f2c
commit
b6cf94ae07
2 changed files with 127 additions and 0 deletions
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@ -643,6 +643,41 @@ static struct mrs_field id_aa64mmfr2_fields[] = {
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/* ID_AA64PFR0_EL1 */
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static struct mrs_field_value id_aa64pfr0_csv3[] = {
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MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""),
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MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_ISOLATED, "CSV3"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64pfr0_csv2[] = {
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MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_NONE, ""),
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MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_ISOLATED, "CSV2"),
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MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "SCXTNUM"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64pfr0_dit[] = {
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MRS_FIELD_VALUE(ID_AA64PFR0_DIT_NONE, ""),
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MRS_FIELD_VALUE(ID_AA64PFR0_DIT_PSTATE, "PSTATE.DIT"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64pfr0_amu[] = {
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MRS_FIELD_VALUE(ID_AA64PFR0_AMU_NONE, ""),
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MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1, "AMUv1"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64pfr0_mpam[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, MPAM, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64pfr0_sel2[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SEL2, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64pfr0_sve[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SVE, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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@ -696,6 +731,12 @@ static struct mrs_field_value id_aa64pfr0_el0[] = {
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};
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static struct mrs_field id_aa64pfr0_fields[] = {
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MRS_FIELD(ID_AA64PFR0, CSV3, false, MRS_EXACT, id_aa64pfr0_csv3),
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MRS_FIELD(ID_AA64PFR0, CSV2, false, MRS_EXACT, id_aa64pfr0_csv2),
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MRS_FIELD(ID_AA64PFR0, DIT, false, MRS_EXACT, id_aa64pfr0_dit),
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MRS_FIELD(ID_AA64PFR0, AMU, false, MRS_EXACT, id_aa64pfr0_amu),
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MRS_FIELD(ID_AA64PFR0, MPAM, false, MRS_EXACT, id_aa64pfr0_mpam),
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MRS_FIELD(ID_AA64PFR0, SEL2, false, MRS_EXACT, id_aa64pfr0_sel2),
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MRS_FIELD(ID_AA64PFR0, SVE, false, MRS_EXACT, id_aa64pfr0_sve),
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MRS_FIELD(ID_AA64PFR0, RAS, false, MRS_EXACT, id_aa64pfr0_ras),
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MRS_FIELD(ID_AA64PFR0, GIC, false, MRS_EXACT, id_aa64pfr0_gic),
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@ -710,7 +751,30 @@ static struct mrs_field id_aa64pfr0_fields[] = {
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/* ID_AA64PFR1_EL1 */
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static struct mrs_field_value id_aa64pfr1_bt[] = {
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MRS_FIELD_VALUE(ID_AA64PFR1_BT_NONE, ""),
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MRS_FIELD_VALUE(ID_AA64PFR1_BT_IMPL, "BTI"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64pfr1_ssbs[] = {
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MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_NONE, ""),
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MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE, "PSTATE.SSBS"),
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MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE_MSR, "PSTATE.SSBS MSR"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64pfr1_mte[] = {
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MRS_FIELD_VALUE(ID_AA64PFR1_MTE_NONE, ""),
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MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL_EL0, "MTE EL0"),
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MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL, "MTE"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field id_aa64pfr1_fields[] = {
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MRS_FIELD(ID_AA64PFR1, BT, false, MRS_EXACT, id_aa64pfr1_bt),
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MRS_FIELD(ID_AA64PFR1, SSBS, false, MRS_EXACT, id_aa64pfr1_ssbs),
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MRS_FIELD(ID_AA64PFR1, MTE, false, MRS_EXACT, id_aa64pfr1_mte),
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MRS_FIELD_END,
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};
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@ -744,6 +808,13 @@ static struct mrs_user_reg user_regs[] = {
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.offset = __offsetof(struct cpu_desc, id_aa64pfr0),
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.fields = id_aa64pfr0_fields,
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},
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{ /* id_aa64pfr0_el1 */
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.reg = ID_AA64PFR1_EL1,
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.CRm = 4,
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.Op2 = 1,
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.offset = __offsetof(struct cpu_desc, id_aa64pfr1),
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.fields = id_aa64pfr1_fields,
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},
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{ /* id_aa64dfr0_el1 */
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.reg = ID_AA64DFR0_EL1,
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.CRm = 5,
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@ -517,6 +517,62 @@
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#define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK)
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#define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT)
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#define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT)
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#define ID_AA64PFR0_SEL2_SHIFT 36
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#define ID_AA64PFR0_SEL2_MASK (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT)
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#define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK)
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#define ID_AA64PFR0_SEL2_NONE (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT)
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#define ID_AA64PFR0_SEL2_IMPL (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT)
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#define ID_AA64PFR0_MPAM_SHIFT 40
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#define ID_AA64PFR0_MPAM_MASK (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT)
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#define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK)
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#define ID_AA64PFR0_MPAM_NONE (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT)
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#define ID_AA64PFR0_MPAM_IMPL (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT)
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#define ID_AA64PFR0_AMU_SHIFT 44
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#define ID_AA64PFR0_AMU_MASK (UL(0xf) << ID_AA64PFR0_AMU_SHIFT)
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#define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK)
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#define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT)
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#define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT)
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#define ID_AA64PFR0_DIT_SHIFT 48
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#define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT)
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#define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK)
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#define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT)
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#define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT)
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#define ID_AA64PFR0_CSV2_SHIFT 56
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#define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT)
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#define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK)
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#define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT)
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#define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT)
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#define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT)
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#define ID_AA64PFR0_CSV3_SHIFT 60
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#define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT)
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#define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK)
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#define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT)
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#define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT)
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/* ID_AA64PFR1_EL1 */
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#define ID_AA64PFR1_EL1 MRS_REG(3, 0, 0, 4, 1)
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#define ID_AA64PFR1_BT_SHIFT 0
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#define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT)
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#define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK)
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#define ID_AA64PFR1_BT_NONE (UL(0x0) << ID_AA64PFR1_BT_SHIFT)
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#define ID_AA64PFR1_BT_IMPL (UL(0x1) << ID_AA64PFR1_BT_SHIFT)
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#define ID_AA64PFR1_SSBS_SHIFT 4
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#define ID_AA64PFR1_SSBS_MASK (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT)
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#define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK)
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#define ID_AA64PFR1_SSBS_NONE (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT)
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#define ID_AA64PFR1_SSBS_PSTATE (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT)
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#define ID_AA64PFR1_SSBS_PSTATE_MSR (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT)
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#define ID_AA64PFR1_MTE_SHIFT 8
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#define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT)
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#define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK)
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#define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT)
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#define ID_AA64PFR1_MTE_IMPL_EL0 (UL(0x1) << ID_AA64PFR1_MTE_SHIFT)
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#define ID_AA64PFR1_MTE_IMPL (UL(0x2) << ID_AA64PFR1_MTE_SHIFT)
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#define ID_AA64PFR1_RAS_frac_SHIFT 12
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#define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT)
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#define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK)
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#define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
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#define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
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/* MAIR_EL1 - Memory Attribute Indirection Register */
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#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
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