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uart: Ingore pl011 historic mistakes
Some veresions of EDK-II and QEMU reported the wrong values for the register shift and the region I/O size. Detect those and set it to the correct values. In general, anything other than a shift of 2 and a regio width of 4 (bytes, or 32 bits) is a mistake. However, allow for overrides in the future by only overriding the buggy values. Otherwise, we will fail to boot. PR: 282936 Sponsored by: Netflix Reviewed by: emaste Differential Revision: https://reviews.freebsd.org/D47946
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1 changed files with 23 additions and 1 deletions
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@ -172,6 +172,27 @@ static int
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uart_pl011_probe(struct uart_bas *bas)
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{
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/*
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* Versions of QEMU before 41f7b58b634e (8.3) reported bogus values for
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* this tabel. The PL011 IP is always 32-bits wide and should be shifted
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* 2 to match the 4-byte size of the data. QEMU reported these values
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* incorrectly before that.
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* https://github.com/qemu/qemu/commit/41f7b58b634ec3b60ae874375d2bbb61d790971e
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*
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* In additon, other hardware vendors also reported this value
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* incorrectly. It's not tied to what the ACPI device node is, but was a
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* misunderstanding coupled with a Linux driver that didn't need the
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* right values. Quirks used to be used to ignore the bad values, now we
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* detect the historic mistake and override (to allow for a future where
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* we may need to override these values).
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*
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* PL011 Docs: https://developer.arm.com/documentation/ddi0183/latest/
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*/
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if (bas->regshft == 0 || bas->regiowidth == 1) {
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bas->regshft = 2;
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bas->regiowidth = 4;
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}
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return (0);
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}
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@ -356,7 +377,8 @@ static struct uart_class uart_pl011_class = {
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.uc_ops = &uart_pl011_ops,
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.uc_range = 0x48,
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.uc_rclk = 0,
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.uc_rshift = 2
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.uc_rshift = 2,
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.uc_riowidth = 4,
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};
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UART_CLASS(uart_pl011_class);
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