For all Marvell devices, MBUS windows configuration is done
in a common place. Only CESA was an exception, so move its
related code from driver to mv_common.c. This way it uses
same proper DRAM information, same as all other interfaces
instead of parsing DT /memory node directly.
Submitted by: Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10723
Commit r312743 ("Use SoC ID - based detection in CESA") resulted
in build failing for Marvell armv5 platforms, which don't support
the newer version of CESA controller. This patch provides a fix by
removing ifdefs around bitfields' definitions, so that they are
known to all platforms.
Submitted by: Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
This commit introduces following changes in order to get rid of
ifdef's from all around the driver.
* Introduce sc_soc_id field in cesa_softc structure - this value is
obtained in cesa_attach() anyway, so make use of it.
* Replace ifdefs with SoC ID checks.
* Perform PM control status only for relevant SoC's.
Submitted by: Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: zbb
Differential revision: https://reviews.freebsd.org/D9247
Improvements after r301220.
Bus space methods are not called so simple pmap_mapdev will suffice.
Use OF_getencprop to get buffer with already converted endianess.
Pointed out by: ian
Submitted by: Michal Stanek <mst@semihalf.com>
Obtained from: Semihalf
Only HMAC-SHA256 is added as it is the only SHA-2 variant supported by
cryptodev. It is not possible to register hardware support for other
algorithms in the family including regular non-keyed SHA256.
Submitted by: Michal Stanek <mst@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D6219
The output of HMAC was previously truncated to 12 bytes. This was only
correct in case of one particular crypto client - the new version of IPSEC.
Fix by taking into account the cri_mlen field in cryptoini session request
filled in by the client.
Submitted by: Michal Stanek <mst@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D6218
TDMA and CESA registers are placed in different ranges of memory. Split
memory resource in DTS to reflect that. This change is needed to support
multiple CESA nodes as otherwise the ranges of different nodes would
overlap.
In consequence, CESA_WRITE and CESA_READ macros have been split depending
on which range of registers is accessed. Offsets for CESA registers have
been modified as the base address has changed.
Submitted by: Michal Stanek <mst@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D6217
On other platforms with CESA accelerator the SRAM memory is mapped in
early init before driver is attached. This method only works correctly
with mappings no smaller than L1 section size (1MB). There may be more
SRAM blocks and they may have smaller sizes than 1MB as is the case
for Armada38x. Instead, map SRAM memory with bus_space_map() in CESA
driver attach. Note that we can no longer assume that VA == PA for the
SRAM.
Submitted by: Michal Stanek <mst@semihalf.com
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D6215
to driver specific files.
- window initialization is done during device attach
- CESA TDMA decoding windows values are set based on DTS,
not copied from CPU registers
- remove unnecessary virtual mapping
- update dts file
Obtained from: Semihalf
