* remove the DEBUG ifdef; defining it is too far reaching throughout
the whole system;
* add a bitmask in the softc for controlling debugging;
* .. enable said debugging as a sysctl;
* add bitmaps for register access, reset and vlans.
TODO:
* Now that the debug statements are configurable, we definitely could
do with more debugging
* Move the debugging into the top-level etherswitch driver and have
sub-drivers obey.
This is slightly different to the other switches - the VLAN table
(VTU) programs in the vlan port mapping /and/ the port config
(tagged, untagged, passthrough, any.)
So:
* Add VTU operations to program the VTU (vlan table)
* abstract out the mirror-disable function so it's .. well, a function.
* setup the port to have a dot1q configuration for dot1q - the
port security is VLAN (not per-port VLAN) and requires an entry
in the VLAN table;
* add set_dot1q / get_dot1q to program the VLAN table;
* since the tagged/untagged ports are now programmed into the VTU,
rather than global - plumb the ports /and/ untagged ports bitmaps
through the arswitch API.
Tested:
* AP135 - QCA9558 SoC + AR8327N switch
All the per-port support is really doing is applying a port visibility
mask to each of the switchports. Everything still look like a single
portgroup (vlan id 1), but the per-port visibility mask is modified.
Whilst I'm here, also add some initial dot1q support - the pvid stuff
is doing the right thing, but it's not useful without the rest of
the VLAN table programming.
It's enough for me to be able to use the LAN/WAN port distinction
on the AP135, where there isn't (for now!) a dedicated PHY for the
"WAN" port.
Tested:
* AP135, QCA9558 SoC + AR8327 switch
* Even though I got the registers around "right", it seems
I'm not tickling the MDIO access correctly for the internal PHY
bus. Some of the switches are fine poking at the external PHY
registers; others aren't. So, enable direct PHY bus access
for the AR8327, and leave the existing code in place for the
others.
* Go and shuffle the register access around. Whilst here,
restore the 2ms delay if changing page.
* Comment out some of the stub printf()s; there's some upcoming
work to add port VLAN support.
Tested:
* AP135 development board
* Carambola2 - AR9331 SoC
The OpenWRT AR8xxx switch support flushes the ATU (address translation
unit) after each port link 'up' status change. I've modified this to
just flush on any port transition.
Whilst here, bump the number of ports on the AR8327 to 6, rather than
the default of 5. It's DB120 specific; I'll go and make this configurable
later.
There's some debugging code in here still; I am still debugging whether
this is or isn't working fully.
Tested:
* DB120, AR9344 + AR8327 switch
Obtained from: OpenWRT
It's still hardcoded (for db120) but it is now hardcoded in all the
same place (ie, the pdata path.) The port config/status code now checks
port0/port6 as appropriate to configure things.
Tested:
* Qualcomm Atheros DB120, AR8327 switch.
switches.
* Add some new VLAN HAL methods that will be used by the VLAN configuration
code. The AR933x and later switches use slightly different register
layouts (even though the driver currently doesn't support it.)
The registers (and perhaps the flags) are different for the AR8327, so
I'll stub those out until they're written.
Tested:
* DB120 - both on-chip AR9340 and AR8327 switches.
* Add an AR9340 switch version entry;
* Support the switch being connected via MII;
* Add a flag to note that a switch is actually an internal
switch rather than an external switch.
Now:
* The ar9340 switch can interconnect via MII;
* Since some slightly different phy/switch register access methods
and quirks appear for the internal versus external switch,
we will need a flag to mark it as an "internal" switch.
Tested:
* AR9344 (internal switch)
* AR9331 (internal switch)
TODO:
* Test the AR8316 switch!
arswitch_writereg() routine was writing the registers in the wrong order.
Revert -r241918 as the root problem is now fixed. Remove another workaround
from arswitch_ar7240.c.
Simplify and fix the code on arswitch_writephy() by using
arswitch_writereg().
While here remove a redundant declaration from arswitchvar.h.
Approved by: adrian (mentor)
* Add in the AR724x support. It probes the same as an AR8216/AR8316, so
just add in a hint to force the probe success rather than auto-detecting
it.
* Add in the missing entries from conf/files, lacking in the previous
commit.
The register values and CPU port / mirror port initialisation value was
obtained from Linux OpenWRT ag71xx_ar7240.c.
The DELAY(1000) to let things settle is my local workaround. For some
reason, PHY4 doesn't seem to probe very reliably without it. It's quite
possible that we're missing some MDIO bus initialisation code in if_arge
for the AR724x case. As I dislike DELAY() workarounds in general, it's
definitely worth trying to figure out why this is the case.
Tested on: AP93 (AR7240) reference design
Obtained from: Linux OpenWRT
This is designed to support the very basic ethernet switch chip behaviour,
specifically:
* accessing switch register space;
* accessing per-PHY registers (for switches that actually expose PHYs);
* basic vlan group support, which applies for the rtl8366 driver but not
for the atheros switches.
This also includes initial support for:
* rtl8366rb support - which is a 10/100/1000 switch which supports
vlan groups;
* Initial Atheros AR8316 switch support - which is a 10/100/1000 switch
which supports an alternate vlan configuration (so the vlan group
methods are stubbed.)
The general idea here is that the switch driver may speak to a variety of
backend busses (mdio, i2c, spi, whatever) and expose:
* If applicable, one or more MDIO busses which ethernet interfaces can
then attach PHYs to via miiproxy/mdioproxy;
* exposes miibusses, one for each port at the moment, so ..
* .. a PHY can be exposed on each miibus, for each switch port, with all
of the existing MII/ifnet framework.
However:
* The ifnet is manually created for now, and it isn't linked into the
interface list, nor can you (currently) send/receive frames on this ifnet.
At some point in the future there may be _some_ support for this, for
switches with a multi-port, isolated mode.
* I'm still in the process of sorting out correct(er) locking.
TODO:
* ray's switch code in zrouter (zrouter.org) includes a much more developed
newbus API that covers the various switch methods, as well as a
capability API so drivers, the switch layer and the userland utility
can properly control the subset of supported features.
The plan is to sort that out later, once the rest of ray's switch drivers
are brought over and extended to export MII busses and PHYs.
Submitted by: Stefan Bethke <stb@lassitu.de>
Reviewed by: ray
