Do not ignore device interrupt if bus mastering is still active. It is
normal in case of media read error and some ATAPI cases, when transfer size
is unknown beforehand. PCI ATA BM specification tells that in case of such
underrun driver should just manually stop DMA engine. DMA engine should
same time guarantie that all bus mastering transfers completed at the moment
of driver reads interrupt flag asserted.
This change fixes interrupt storms and command timeouts in many cases.
PR: kern/103602, sparc64/121539, kern/133122, kern/139654
On Soft Reset, read device signature from FIS receive area, instead of
PxSIG register. It works better for NVidia chipsets. ahci(4) does the same.
PR: kern/140472, i386/138668
Explicitly acknowledge MSI completion, as required by SiI3124 datasheet.
It makes MSI working there. Later (and cheaper) PCIe chips (3132/3531)
still randomly crashing system in few seconds of high MSI rates, generating
something inaporopriate, like NMI or "Fatal trap 30".
Add Asynchronous Notification support for controllers without SNTF
capability by snooping SDB FIS receive area. It should be even faster
then regular way, but less reliable.
r199237:
sc->rev and is_offload(sc) will always be 0 during probe. Wait till
attach to get correct values.
r199238:
Make sure *some* edc is setup even for an unknown transceiver (assume
it is optical).
r199239:
The 10GBASE-T card should use an IPG of 1. Also enable the check
for low power startup on this card.
r199240:
Don't disable the XGMAC's tx on ifconfig down. It is unnecessary
and can cause false backpressure in the chip. Fix a us/ms mixup
while here.
r200003:
T3 firmware 7.8.0 for cxgb(4)
lindev(4) [1] is supposed to be a collection of linux-specific pseudo
devices that we also support, just not by default (thus only LINT or
module builds by default).
While currently there is only "/dev/full" [2], we are planning to see more
in the future. We may decide to change the module/dependency logic in the
future should the list grow too long.
This is not part of linux.ko as also non-linux binaries like kFreeBSD
userland or ports can make use of this as well.
Suggested by: rwatson [1] (name)
Submitted by: ed [2]
Discussed with: markm, ed, rwatson, kib (weeks ago)
Reviewed by: rwatson, brueffer (prev. version)
PR: kern/68961
Drop USB mass storage devices support from ata(4). It is out of the build as
long as I remember, and completely superseded by better maintained umass(4).
It's main idea was to optionally avoid CAM dependency for such devices, but
with move ATA to CAM, it is not actual any more.
No objections: hselasky@, thompsa@, arch@
- Extend XPT-SIM transfer settings control API. Now it allows to report to
SATA SIM number of tags supported by each device, implement ATA mode and
SATA revision negotiation for both SATA and PATA SIMs.
- Make ahci(4) and siis(4) to use submitted maximum tag number, when
scheduling requests. It allows to support NCQ on devices with lower tags
count then controller supports.
- Make PMP driver to report attached devices connection speeds.
- Implement ATA mode negotiation between user settings, device and
controller capabilities.
- Improve ATA mode/SATA revision control.
- fix a LOR between process lock and pmc thread mutex
- fix a system deadlock on process exit when the sample buffer
is full (pmclog_loop blocked in fo_write) and pmcstat exit.
It seems generation of link state change of e1000phy(4) is not
reliable on some Marvell PHYs. If msk(4) know it still does not
have established link check whether msk(4) missed the link state
change by looking into polled link state.
Reported by: Mel Flynn < mel.flynn+fbsd.current <> mailing.thruhere dot net >,
Gleb Kurtsou <gleb.kurtsou <> gmail dot com >
Tested by: Gleb Kurtsou <gleb.kurtsou <> gmail dot com >
r198996:
Remove unnecessary header file.
r198997:
It's normal to see Rx FIFO overruns under high network load and
showing the message creates other side-effects. Remove the Rx
FIFO overrun message in interrupt handler. msk(4) should recover
from the FIFO overruns without any user intervention. Users can
still check the Rx FIFO overrun counter from MAC MIB statistics
maintained in driver(dev.msk.0.stats.rx.overflows).
Add a check to know whether driver is still running after
reacquiring driver lock in Rx handler. re(4) drops a driver lock
before passing received frame to upper stack and reacquire the
lock. During the time window ioctl calls could be executed and if
the ioctl was interface down request, driver will stop the
controller and free allocated mbufs. After that when driver comes
back to Rx handler again it does not know what was happend so it
could access free mbufs which in turn cause panic.
Reported by: Norbert Papke < npapk <> acm dot org >
Tested by: Norbert Papke < npapk <> acm dot org >
For AR8132 fast ethernet controller, do not report 1000baseT
capability to mii(4). Even though AR8132 uses the same model/
revision number of F1 gigabit PHY, the PHY has no ability to
establish 1000baseT link. I have no idea why Atheros use the same
device/model id for this PHY.
With this change atphy(4) does not report 1000baseT media
capability and manual 1000baseT configuration is also disabled
which is more desirable behavior for 10/100Mbps PHY.
Add DGE-560SX(Yukon XL) to the supported device list. Many thanks
to "Eugene Perevyazko <john <> dnepro dot net>" who kindly gave
remote access to system with DGE-560SX.
Add hack to pass controller specific information to phy driver.
Unlike most other PHYs there is no easy way to know which media
type the PHY supports on Marvell PHYs. MIIF_HAVEFIBER flags is now
passed via bus-specific instance variable of a device. While I'm
here add 88E1112 specific work around to set SIGDET polarity low.
Many thanks "Eugene Perevyazko <john <> dnepro dot net>" who kindly
gave remote access to system with DGE-560SX.
Add sysctls in ahd(4) in order to keep track of different classes of
errors. So far 3 different classes are present (correctable,
uncorrectable and fatal) but more can be added easilly.
Sponsored by: Sandvine Incorporated
Introduce hw.hptrr.attach_generic loader tunable to deny hptrr driver
attach chips with generic Marvell (non-HighPoint) PCI identification.
These chips are also supported by ata(4). Some vendors, like Supermicro,
are using same chips without providing HPT RAID BIOS.
PR: kern/120842, kern/136750
Fix Intel PATA UDMA timings setting, affecting write performance.
Binary divider value 10 specified in datasheet is not a hex 0x10.
UDMA2 should be 33/2 instead of 66/4, which is documented as reverved,
UDMA4 should be 66/2 instead of 66/4, which is definitely wrong.
Release over-agressive WDMA0 mode timings as close to spec as chip can.
Use only lower byte of sectors_intr IDENTIFY word as sector count.
This fixes SET_MULTI error during boot on devices supporting less then
16 sectors per interrupt.
Do not attach JMicrons with single PCI function. They are not working as
AHCI for some reason, even when declaring so. Let atajmicron configure
them for us and provide PATA support.
- Add some bits of HDMI/DisplayPort support from later specification updates.
It may be not enough to make them work, but at least should give some
information about these beasts.
- Add Realtek ALC887 codec ID.
Change the way in which AHCI+PATA combined controllers, such as JMicron
are handled. Instead of trying to attach two different drivers to
single device, wrapping each call, make one of them (atajmicron)
attach do device solely, but create child device for AHCI driver,
passing it all required resources. It is quite easy, as none of
resources are shared, except IRQ.
Add support for AHCI SATA parts of alike SATA+PATA MArvell controllers.
Add IDs of Marvell 88SX6102, 88SX6111. 88SX6141 controllers.
As result, it:
- makes drivers operation more independent and straitforward,
- allows to use new ahci(4) driver with such devices, adding support for
new features, such as PMP and NCQ, same time keeping legacy PATA support,
- will allow to just drop old ataahci driver, when it's time come.
- Remove most of direct relations between ATA(4) peripherial and controller
levels. It makes logic more transparent and is a mandatory step to wrap
ATA(4) controller level into ATA-native CAM SIM.
- Tune AHCI and SATA2 SiI drivers memory allocation a bit to allow bigger
I/O transaction sizes without additional cost.
