Add support for SATA part of Marvell 88SE912x controllers to ahci(4).
Limit early revisions from 6Gb/s to 3Gb/s by default, or they negotiate
only 1.5Gb/s, when 3Gb/s devices connected.
Add dummy driver for PATA part of these controllers, preventing generic
driver attach them. It causes system freeze when SATA controller used after
PATA was touched.
201408,201325,200089,198822,197373,197372,197214,196162). Since one of those
changes was a semicolon cleanup from somebody else, this touches a lot more.
o Properly support M5229 revision 0xc7 and 0xc8:
- These revisions no longer have cable detection capability.
- The UDMA support bit of register 0x4b has been dropped without an
replacement.
- According to Linux it's crucial for working ATAPI DMA support to
also set the reserved bit 1 of regsiter 0x53 with these revisions.
o Only set ATA_CHECKS_CABLE for chip versions that actually support
cable detection, i.e. neither for ALI_OLD nor for ALI_NEW revisions
>= 0xc7.
Unbreak the ata_atapi() usage. Since r200171 (MFC'ed in r200432) the
mode setting functions get a ata_device type device passed instead of
a ata_channel one, thus ata_atapi() has to be adjusted accordingly.
Reviewed by: mav
Large I/Os on Promise controllers reported to cause UDMA ICRC errors and
subsequent timeouts. Restore previous limit for now, at least until
I will have hardware to experiment.
PR: kern/141438
Introduce ATA_CAM kernel option, turning ata(4) controller drivers into
cam(4) interface modules. When enabled, this option deprecates all ata(4)
peripheral drivers (ad, acd, ...) and interfaces and allows cam(4) drivers
(ada, cd, ...) and interfaces to be natively used instead.
As side effect of this, ata(4) mode setting code was completely rewritten
to make controller API more strict and permit above change. While doing
this, SATA revision was separated from PATA mode. It allows DMA-incapable
SATA devices to operate and makes hw.ata.(ata|atapi)_dma tunable work again.
Also allow ata(4) controller drivers (except some specific or broken ones)
to handle larger data transfers. Previous constraint of 64K was artificial
and is not really required by PCI ATA BM specification or hardware.
Submitted by: nwitehorn (powerpc part)
On Soft Reset, read device signature from FIS receive area, instead of
PxSIG register. It works better for NVidia chipsets. ahci(4) does the same.
PR: kern/140472, i386/138668
Fix Intel PATA UDMA timings setting, affecting write performance.
Binary divider value 10 specified in datasheet is not a hex 0x10.
UDMA2 should be 33/2 instead of 66/4, which is documented as reverved,
UDMA4 should be 66/2 instead of 66/4, which is definitely wrong.
Release over-agressive WDMA0 mode timings as close to spec as chip can.
Change the way in which AHCI+PATA combined controllers, such as JMicron
are handled. Instead of trying to attach two different drivers to
single device, wrapping each call, make one of them (atajmicron)
attach do device solely, but create child device for AHCI driver,
passing it all required resources. It is quite easy, as none of
resources are shared, except IRQ.
Add support for AHCI SATA parts of alike SATA+PATA MArvell controllers.
Add IDs of Marvell 88SX6102, 88SX6111. 88SX6141 controllers.
As result, it:
- makes drivers operation more independent and straitforward,
- allows to use new ahci(4) driver with such devices, adding support for
new features, such as PMP and NCQ, same time keeping legacy PATA support,
- will allow to just drop old ataahci driver, when it's time come.
- Remove most of direct relations between ATA(4) peripherial and controller
levels. It makes logic more transparent and is a mandatory step to wrap
ATA(4) controller level into ATA-native CAM SIM.
- Tune AHCI and SATA2 SiI drivers memory allocation a bit to allow bigger
I/O transaction sizes without additional cost.
Add support for different request block format used by Gen-IIe Marvell SATA.
This adds support for Marvell 6042/7042 chips and Adaptec 1430SA controller.
MFC r198718:
Allow newly added controllers to use full I/O sizes.
- Revert r191568 partially. Forcing AHCI mode by changing device subclass
and progif is evil. It doesn't work reliably[1] and we should honor BIOS
configuration by the user.
- If the SATA controller is enbled but combined mode is disabled, mask off
the emulated IDE channel on the legacy IDE controller.
Pointed out by: mav[1]
the work area was totally unsynchronized which means this driver only
had a chance of working on x86 when no bounce buffers were involved,
which isn't that likely given that support for 64-bit DMA is currently
broken throughout ata(4).
- Add necessary little-endian conversion of accesses to the work area,
making this driver work on big-endian hosts. While at it, use the
alignment-agnostic byte order encoders in order to be on the safe side.
- Clear the reserved member of the SG list entries in order to be on the
safe side. [1]
Submitted by: yongari [1]
Reviewed by: yongari
Approved by: re (kib)
MAXPHYS. Current ataahci driver memory allocation scheme includes only
64 items in DMA S/G table, and so not guarantied to support transactions
with more then 252K data.
Approved by: re (kensmith)
MFC after: 2 weeks
routine and save the resources using a chipset-data structure. Use these
preallocated resources to setup resources for the SATA channels to avoid
asking the PCI bus to allocate the same BAR multiple times.
Tested by: bms
MFC after: 1 week
chipset-specific code to attach chipset-specific data.
- Use chipset-specific data in the acard and promise chipsets rather than
changing the ivars of ATA PCI devices. ivars are reserved for use by the
parent bus driver and are _not_ available for use by devices directly.
This fixes a panic during sysctl -a with certain Promise controllers with
ACPI enabled.
Reviewed by: mav
Tested by: Magnus Kling (kingfon @ gmail) (on 7)
MFC after: 3 days
Feature is controlled by hint.ata.X.pm_level tunable:
0 - PM disabled, old behaviour, default.
1 - device is allowed to initiate PM state change, host is passive.
2 - host initiates PARTIAL state transition every time port is idle.
3 - host initiates SLUMBER state transition every time port is idle.
PARTIAL state has up to 100us (50us for me) wakeup latency, but for my
ICH8M saves 0.5W of power per drive. SLUMBER state has up to 10ms (3.5ms
for me) wakeup latency, but saves 0.8W of power.
Modes 2 and 3 are implemented only for AHCI driver now.
Interface power management is incompatible with device presence detection
(host receives no signal from drive, so unable to monitor it), so later is
disabled when PM is used.
controllers may be configured as legacy IDE mode by modifying subclass and
progif without actually changing PCI device IDs. Instead of complicating
code, we always force AHCI mode while probing. Also we restore AHCI mode
while resuming per ATI/AMD register programming/requirement guides.
- Fix SB700/800 "combined" mode. Unlike SB600, this PATA controller can
combine two SATA ports and emulate one PATA channel as primary or secondary
depending on BIOS configuration. When the combined mode is disabled, this
channel disappears and it works just like SB600 PATA controller, however.
- Add more PCI device IDs for SB700/800 and adjust device descriptions.
SB800 shares the same PCI device IDs and added two more SATA IDs.
the ATA status register with a 4-byte read request. This updates it, and
subsequent 1-byte reads will return the correct result.
This commit adds a hack to do this, which is currently ifdef'd powerpc,
although Linux and Darwin do this unconditionally on all platforms.
