checksum header. The header contains a received frame length but
the defined length for AX88772B is different with other ASIX
controllers. When the RX checksum is off, AX88772B controller does
not prepend a checksum header so driver has to use normal header
length mask.
This change should fix RX errors when RX checksum offloading is
off.
Tested by: kevlo
MFC After: 1 week
generic mii_phy_reset().
- Return the result of mii_mediachg() rather than blindly returning 0.
- on smsc(4), driver lock should be held to get current
mii_media_active/mii_media_status value.
Reviewed by: yongari
Realtek RTL8188CU/RTL8192CU USB IEEE 802.11b/g/n wireless cards.
This driver requires microcode which is available in FreeBSD ports:
net/urtwn-firmware-kmod.
Hiren ported the urtwn(4) man page from OpenBSD and Glen just commited a port
for the firmware.
TODO:
- 802.11n support
- Stability fixes - the driver can sustain lots of traffic but has trouble
coping with simultaneous iperf sessions.
- fix debugging
MFC after: 2 months
Tested by: kevlo, hiren, gjb
1) Only multi-TD isochronous transfers should use NORMAL
type after specific type as per XHCI specification.
2) BEI bit is only available in NORMAL and ISOCHRONOUS
TRB types. Don't use this bit for other types to avoid
hardware asserts. Reserved bits should be don't care
though ...
MFC after: 1 week
PR: usb/179342
the regular interrupt handler is not working properly or
in case of MSI interrupts which are not yet supported.
Remove interrupt setup code for FreeBSD versions older
than 700031.
MFC after: 1 week
PR: usb/179342
controller hardware most likely present on UHCI chipsets aswell. The
bug manifests itself when issuing isochronous transfers and bulk
transfers towards the same device simultaneously. From time to time it
happens that either the completion IRQ was missing or that the
completion IRQ was happening before the ITD/SITD was completely
written back to memory. The workaround assumes that double buffered
isochronous transfers are used, and that a second interrupt is
generated at the beginning of the next isochronous transfer to
complete the previous one. Possibly skipping the interrupt at the last
isochronous frame is possible, but will then break single buffered
isochronous transfers. For now we can live with some extra interrupts.
MFC after: 1 week
o The CP2101 and CP2102 do not support GPIO pin use at all, enforce this.
o Support reading the GPIO status on the second port of the CP2105. More
work is needed before the CP2105 GPIO pins can be used as outputs.
Hardware donated by: Silicon Labs
MFC after: 3 weeks
in reduced memory systems.
- Split allocation and freeing of the configuration descriptor into a separate
function, so that the configuration descriptor can be made fixed size
to save memory allocations. This applies for both device and host mode.
