- Put "_LE_" into the register access macros to indicate little endian
byte order is expected by the hardware.
- Avoid using the bounce buffer when not strictly needed. Try to move
data directly using bus-space functions first.
- Ensure we preserve the reserved bits in the power down mode
register. Else the hardware goes into a non-recoverable state.
- Always use 32-bit access when writing or reading registers or FIFOs,
because the hardware is 32-bit oriented and don't really understand 8-
and 16-bit access.
- Correct writes to the memory address register. There is no need to
shift the register offset.
- Correct interval for interrupt endpoints.
- Optimise 90ns internal memory buffer read delay.
- Rename PDT into PTD, which is how the datasheet writes it.
- Add missing programming for activating host controller PTDs.
Sponsored by: DARPA, AFRL
direction isochronous transfers.
- Remove setting of fields which does not belong to the respective
TRBs. These fields are currently set as zero and this is more a
cosmetic change.
MFC after: 3 days
Submitted by: Horse Ma <HMa@wyse.com>
- Make sure TX/RX lists don't leak and are only allocated once.
- Fix off-by one transfer index computation.
- Give firmware loading more time.
MFC after: 3 days
be a race when using a single active queue for all transmit types.
- Last argument of usb_pause_mtx() is ticks and not milliseconds.
- Remove unused watchdog.
- Remove some unused fields from the RSU softc structure.
- Workaround usbd_transfer_start() recursion from inside of completion
callback.
MFC after: 3 days
- Need to set the pre-fetch memory address when reading the host memory.
- We currently assume that no endianness conversion is needed.
Sponsored by: DARPA, AFRL
- Implement support for interrupt filters in the DWC OTG driver, to
reduce the amount of CPU task switching when only feeding the FIFOs.
- Add common spinlock to the USB bus structure.
MFC after: 2 weeks
the main processing queue, clear the NAK counter for any associated
BULK or CONTROL transfers and poll the endpoint(s) for 1 millisecond
at 125us rate interval, before going into slow, 10ms, NAK polling mode
again. This has the effect that typical ping-ping protocols respond
quicker when initiated from the USB host.
MFC after: 2 weeks
- For non-periodic traffic we only need to wait two SOFs before
disabling the channel.
- Make sure we release the TX FIFO tracking level after the host
channel is disabled.
- Make sure the host channel state gets reset/disabled initially.
- Two minor code style changes.
MFC after: 2 weeks
- Rework how we allocate and free USB host channels, so that we only
allocate a channel if there is a real packet going out on the USB
cable.
- Use BULK type for control data and status, due to instabilities in
the HW it appears.
- Split FIFO TX levels into one for the periodic FIFO and one for the
non-periodic FIFO.
- Use correct HFNUM mask when scheduling host transactions. The HFNUM
register does not count the full 16-bit range.
- Correct START/COMPLETION slot for TT transactions. For INTERRUPT and
ISOCHRONOUS type transactions the hardware always respects the ODDFRM
bit, which means we need to allocate multiple host channels when
processing such endpoints, to not miss any so-called complete split
opportunities.
- When doing ISOCHRONOUS OUT transfers through a TT send all data
payload in a single ALL-burst. This deacreases the likelyhood for
isochronous data underruns.
- Fixed unbalanced unlock in case of "dwc_otg_init_fifo()" failure.
- Increase interrupt priority.
MFC after: 2 weeks
controller driver by piggybacking the SOF interrupt when issuing new
and checking old transfers. Number of interrupts was reduced by 30%
when doing Isochronous transfers.
Use correct GINTMSK_XXX macros when accessing the DWC OTG interrupt
mask register.
Add code to adjust the frame interval register which influences the
SOF rate.
MFC after: 2 weeks
speed data traffic going directly to a USB device or through a
so-called USB transaction translator.
Add checks that we are not overusing the TX FIFO.
MFC after: 2 weeks
define a few imx_ccm_foo() functions that are implemented by the imx51 or
imx6 ccm code. Of course, the imx6 ccm code is still more a wish than
reality, so for now its implementations just return hard-coded numbers.
a jtag debugging product, which was used on early Beaglebone boards (later
boards used a standard FTDI 2232C product ID). Change the name accordingly,
and also add an entry for XDS100V3, the latest version of that product
which has its own new product ID number.
Device type and revision is now determined from the bcdDevice field and
doesn't need to be in the table at all. The feature that skips creation
of /dev/ttyU* entries for jtag and gpio interfaces is enhanced:
- The feature is now optional, but enabled by default. A tunable and
sysctl are available to control it: hw.usb.uftdi.skip_jtag_interfaces.
- We no longer assume interface #0 is the only jtag interface. Up to
eight interfaces per chip can be flagged as jtag. (Current ftdi chips
support a max of 4 interfaces; this leaves room for growth.)
- Some manufacturers don't change the product ID or use the same ID for
different devices intended for both serial-comms and jtag/gpio use.
Often while the product ID is the same, the product name string is
different, so it's now possible to search for the product name in a
table of strings and get the set of non-tty interfaces from that table.
