Turns out we need all the barrier.
The one before writing the OWN bit is needed so the DMA engine
have coherent data, the second one (after the OWN bit is set) is
also needed because the DMA buffers are allocated with VM_MEMATTR_DEFAULT
whic equals to being cached.
This reverts commit 2b4f615e7d4720b16007cfa8aaedf720f572067a.
This reverts commit 4870346488051b9c4a1dc8b11cab55d4e5b7c230.
Reported by: mmel
We need the DMA engine to have everything coherent *before* we
set the OWN bit (the bit that tells the DMA engine that it owns
the descriptor).
Fixes: 487034648805 ("dwc: Rewrite barrier part")
Reported by: jhb
- Add a txdesc_clear which clears the tx desc instead of doing that in
dwc_setup_txdesc based on arguments.
- Remove dwc_set_owner, in the end we always set the owner of the desc
as we do it for id > 0 and then for the first one.
- Remove dwc_ prefix
No functional changes intended.
This doesn't represent the mac_type but if the DMA engine support
extended descriptors.
Read the HW_FEATURE register to learn if the DMA engine supports it.
No functional changes intended.
And rename it to DMA_DEFAULT_PBL, this is the default for all (most ?)
dma engine that dwc should support.
While here stop including dwc1000_reg.h in if_dwc.c, we don't need it anymore.
No functional changes intended.
Synopsis/Designware controller have multiple version. The version currently
supported by dwc(4) is the version 3 and it's usually called 1000 for gigabit.
In the goal to support all of those in the same base driver start splitting the
core function to a new file.
No functional changes intended.
Synopsis/Designware controller have multiple dma version, the one included
in the driver is the base one. if_awg is one example of a dwc variant that
have another DMA controller. eqos is a newer variant of dwc that have a newer
dma controller.
In the goal to support all of those in the same base driver start splitting the
dma function to a new file.
No functional changes intended.
Synopsis/Designware controller have multiple version. The version currently
supported by dwc(4) is the version 3 and it's usually called 1000 for gigabit.
This file only have definition for the registers of this version so rename it.
No functional changes intended.
snps,dwmac have one required clock named stmmaceth and one optional pclk,
correctly handle both in if_dwc, no need to get/enable stmmacseth again
in if_dwc_rk.
It also have one required reset also named stmmaceth and one optional ahb,
correctly handle both.
Rockchip have another optional clock named clk_mac_speed, get it and enable it
if present. Also fix the optional RMII clocks, they were previously wrongly
enabled in RGMII case.
It makes it easier to find all the sub drivers and change them if needed.
While here do not gate dwc_rk with soc options, dwc_rk is made for all rockchip
SoCs. Same thing for dwc_socfpga
Summary:
These came in the original DrvAPI commits in 2014, and are obsoleted by
bpf_mtap_if() and ether_bpf_mtap_if(). The `_if` suffix, rather than
prefix, conveys that it's operating on the bpf of the interface, instead
than the interface itself.
Reviewed by: glebius
Sponsored by: Juniper Networks, Inc.
Differential Revision: https://reviews.freebsd.org/D41146
It was observed that on RockPro64 hardware, the dwc interface is unable
to receive packets after being assigned a new MAC address. The fix is
simply to call mii_mediachg() before touching any device registers in
dwc_init_locked(). This is consistent with what the OpenBSD driver does.
PR: 263820
MFC after: 1 week
We already increment the unicast IPACKETS and OPACKETS counters in the
rx/tx paths, respectively. Multicast packets are counted in the generic
ethernet code. Therefore, we shouldn't increment these counters in
dwc_harvest_stats().
Drop the early return from dwc_rxfinish_one() so that we still count
received packets with e.g. a checksum error.
PR: 263817
Reported by: Jiahao LI <jiahali@blackberry.com>
Reviewed by: manu
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D35499
We claim support in ifcaps, but don't actually enable it.
PR: 263886
Reviewed by: manu
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D35498
It can be useful for testing.
Reviewed by: manu
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D35496
And if_t rather than struct ifnet *. No functional change intended.
Reviewed by: manu
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D35497
Some board use dwc phy in MII mode, so do not fail to attach if this is
the case.
Only rockchip code uses the phy mode to program some custom syscon register.
PR: 260848
MFC after: 1 week
Sponsored by: Beckhoff Automation GmbH & Co. KG
EXT_RESOURCES have been introduced in 12-CURRENT and all supported
releases have it enabled in their kernel config.
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D33820
Original if_dwc driver used m_defrag as an implementation shortcut but on
1000Mb networks it affects performance. Implement multi-descriptor support for
TX path.
Tested on RK3399-Firefly, patch adds ~15% of network throughput.
Reviewed By: manu
Differential Revision: https://reviews.freebsd.org/D27520
DTS node can have this property which configure the burst length
for both TX and RX if it's the same.
This unbreak if_dwc on Allwinner A20 and possibly other boards that
uses this prop.
Reported by: qroxana <qroxana@mail.ru>
Do not hardcode what we setup for the DMA engine configuration but
lookup the fdt properties and configuring accordingly.
Use a default value of 8 for the burst dma length for both TX and
RX, this is what we used for TX before.
