upstream/opnsense-src
1
0
Fork 0
mirror of https://github.com/opnsense/src.git synced 2026-02-28 20:30:57 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions
253105 commits 28 branches 220 tags 2.1 GiB
Commit graph

3 commits

Author SHA1 Message Date
Ruslan Bukin
33cf9122f3 Add SMP support for BERI CPU. 
Obtained from:	CheriBSD
Sponsored by:	DARPA, AFRL
 2018-04-12 17:43:19 +00:00
Brooks Davis
f66834b69a MFP4: 
Change 228019 by bz@bz_zenith on 2013/04/23 13:55:30

	Add kernel side support for large TLB on BERI/CHERI.
	Modelled similar to NLM

MFC after:	3 days
Sponsored by:	DAPRA/AFRL
 2013-10-22 21:08:25 +00:00
Robert Watson
c9790125b5 Add preliminary support for the SRI International / University of Cambridge 
Bluespec Extensible RISC Implementation (BERI) processor.  BERI is a 64-bit
MIPS ISA soft CPU core that can be synthesised to Altera and Xilinx FPGAs,
and is being used for CPU and OS research at several institutions.

Sponsored by:   DARPA, AFRL
 2012-08-25 08:31:21 +00:00