Commit graph

19 commits

Author SHA1 Message Date
Adrian Chadd
2ba4bf8fa5 [arswitch] Implement the switch MAC address fetch API.
The placeholders are here for some future "set" MAC address API.

Tested:

* AR9340 switch
* AR8327 switch
2018-02-06 08:35:49 +00:00
Adrian Chadd
45a7272a5b [arswitch] fix build breakage.
Apparently the last time I checked building this it didn't pick up that the
header had changed.
2018-02-05 20:30:53 +00:00
Adrian Chadd
7f81a20479 [arswitch] fix mac address field definition.
Whilst here, add some further fields for future experimenting.

Tested:

* AR9340 switch
* AR9330 switch
* AR7240 switch
2018-02-05 07:03:45 +00:00
Adrian Chadd
c9f70b7b88 [arswitch] fix up issues on the AR8327.
This correctly dumps the ethernet bridge contents on an AR8327 switch.

Tested:

* AP135 - QCA9550 + AR8327 ethernet switch:

# etherswitchcfg atu dump
 [0] c0:3f:d5:7e:6f:45: portmask 0x00000004
 [1] f6:b6:03:96:1e:ba: portmask 0x00000004
 [2] 00:03:7f:11:38:4f: portmask 0x00000040
# arp -na
? (192.168.3.170) at 00:03:7f:11:38:4f on arge0 permanent [ethernet]
? (192.168.3.12) at c0:3f:d5:7e:6f:45 on arge0 expires in 1188 seconds [ethernet]
? (192.168.3.1) at f6:b6:03:96:1e:ba on arge0 expires in 1186 seconds [ethernet]
2018-02-04 08:22:11 +00:00
Adrian Chadd
65d59686e1 [arswitch] add initial functionality for AR8327 ATU management.
* Add the bulk of the ATU table read function
* Correct how the ATU function and WAIT bits work

TODO:

* more testing, figure out how the multi-vlan table stuff works and push that
  up to userspace
2018-02-03 00:59:08 +00:00
Adrian Chadd
62042c979d [arswitch] begin tidying up the learning and ATU management, introduce ATU APIs.
* Refactor the initial learning configuration (port learning, address expiry,
  handling address moving between ports, etc, etc) into a separate HAL routine
* and ensure that it's consistent between switch chips - the AR8216,8316,724x,9331
  SoCs all share the same switch code.
* .. the AR8327 needs doing - the defaults seem OK for now
* .. the AR9340 is different but it's also programmed now.

* Add support for flushing a single port worth of ATU entries
* Add support for fetching the ATU table from AR8216 and derived chips

Tested:

* AR9344, Carambola 2

TODO:

* Further testing on other chips
* Add AR9340 support
* Add AR8327 support
2018-02-02 22:05:36 +00:00
Pedro F. Giffuni
718cf2ccb9 sys/dev: further adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.
2017-11-27 14:52:40 +00:00
Adrian Chadd
749cac133f Add per-port vlan support for the AR8327.
All the per-port support is really doing is applying a port visibility
mask to each of the switchports.  Everything still look like a single
portgroup (vlan id 1), but the per-port visibility mask is modified.

Whilst I'm here, also add some initial dot1q support - the pvid stuff
is doing the right thing, but it's not useful without the rest of
the VLAN table programming.

It's enough for me to be able to use the LAN/WAN port distinction
on the AP135, where there isn't (for now!) a dedicated PHY for the
"WAN" port.

Tested:

* AP135, QCA9558 SoC + AR8327 switch
2015-03-08 21:59:03 +00:00
Adrian Chadd
0f3ec57676 Add another register definition for the AR8327.
Obtained from:	OpenWRT
2015-02-28 23:59:29 +00:00
Adrian Chadd
93f5e67e02 Add AR8216 era ATU management/configuration register definitions.
Obtained from:	OpenWRT
2014-03-02 05:47:05 +00:00
Adrian Chadd
ddea319180 Be paranoid about bit operations here. 2014-03-01 00:11:45 +00:00
Adrian Chadd
7307fbd10b The MDIO control register for the AR8327 has a different address to
previous chipsets.

Obtained from:	AR8327 datasheet
2014-02-17 05:54:24 +00:00
Adrian Chadd
7e1a619d03 Implement PHY bus MMD writes for arswitch.
This is used by the AR8327 PHY setup path.

Obtained from:	OpenWRT
2014-02-17 02:24:58 +00:00
Eitan Adler
7a22215c53 Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit.  Instead use (1U << 31) which gets the
expected result.

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.

Discussed with:	-arch, rdivacky
Reviewed by:	cperciva
2013-11-30 22:17:27 +00:00
Adrian Chadd
7e57b3ad31 Add AR934x, AR8327 register definitions.
Obtained from:	Linux/OpenWRT
2013-10-15 00:26:02 +00:00
Luiz Otavio O Souza
b9f07b864b Add the support for 802.1q and port based vlans for arswitch.
Tested on: RB450G (standalone ar8316), RSPRO (standalone ar8316) and
TPLink MR-3220 (ar724x integrated switch).

Approved by:	adrian (mentor)
Obtained from:	zrouter
2013-07-23 14:24:22 +00:00
Adrian Chadd
2015605e8d * Add in the AR7240 global control field for setting the maximum frame
size for the AR7240.

* Include SM/MS macros, thanks to ath_hal(4).

* This field is for normal packets, VLAN and other headers are added to
  this by the switch device.

* Set the MTU to 1536, to match what is done in Linux.  Use the SM
  macro to write this field.

Obtained from:	Atheros (AR7240 datasheet), Linux OpenWRT (MTU default)
2012-05-12 20:36:12 +00:00
Adrian Chadd
67a8db4dba * Remove the AR7240 register defines and reuse the AR8x16 defines.
* Include a new register define to represent "disable port mirroring
  to CPU port".

Obtained from:	Patrick Kelsey <kelsey@ieee.org>
2012-05-12 06:24:21 +00:00
Adrian Chadd
a043e8c76b Commit the first pass of the etherswitch support.
This is designed to support the very basic ethernet switch chip behaviour,
specifically:

* accessing switch register space;
* accessing per-PHY registers (for switches that actually expose PHYs);
* basic vlan group support, which applies for the rtl8366 driver but not
  for the atheros switches.

This also includes initial support for:

* rtl8366rb support - which is a 10/100/1000 switch which supports
  vlan groups;
* Initial Atheros AR8316 switch support - which is a 10/100/1000 switch
  which supports an alternate vlan configuration (so the vlan group
  methods are stubbed.)

The general idea here is that the switch driver may speak to a variety of
backend busses (mdio, i2c, spi, whatever) and expose:

* If applicable, one or more MDIO busses which ethernet interfaces can
  then attach PHYs to via miiproxy/mdioproxy;

* exposes miibusses, one for each port at the moment, so ..

* .. a PHY can be exposed on each miibus, for each switch port, with all
  of the existing MII/ifnet framework.

However:

* The ifnet is manually created for now, and it isn't linked into the
  interface list, nor can you (currently) send/receive frames on this ifnet.
  At some point in the future there may be _some_ support for this, for
  switches with a multi-port, isolated mode.

* I'm still in the process of sorting out correct(er) locking.

TODO:

* ray's switch code in zrouter (zrouter.org) includes a much more developed
  newbus API that covers the various switch methods, as well as a
  capability API so drivers, the switch layer and the userland utility
  can properly control the subset of supported features.

  The plan is to sort that out later, once the rest of ray's switch drivers
  are brought over and extended to export MII busses and PHYs.

Submitted by:	Stefan Bethke <stb@lassitu.de>
Reviewed by:	ray
2012-05-11 20:53:20 +00:00