Add a driver by Fredrik Lindberg for Option HSDPA USB devices. These differ
from standard 3G wireless units by supplying a raw IP/IPv6 endpoint rather than
using PPP over serial. uhsoctl(1) is used to initiate and close the WAN
connection.
Obtained from: Fredrik Lindberg <fli@shapeshifter.se>
Adjust a comment to reflect reality, as we have proper source
address selection, even for IPv4, since r183571.
Pointed out by: Jase Thew (bazerka beardz.net)
Add comments trying to explain what bad things happen here, i.e.
how hashed MD5/SHA are implemented, abusing Final() for padding and
sw_octx to transport the key from the beginning to the end.
Enlightened about what was going on here by: cperciva
Reviewed by: cperciva
After adding an SDT provider for opencrypto in r199884 we should also
depend on opt_kdtrace.h for the module build.
Submitted by: (Andre.Albsmeier siemens.com)
As nfsm_srvmtofh_xx() assumes the 4-byte alignment required by XDR
ensure the mbuf data is aligned accordingly by calling nfs_realign()
in fha_extract_info(). This fix is orthogonal to the problem solved
by r199274/r199284 (MFC'ed to stable/8 in r199733).
PR: 142102 (second part)
While AHCI specification tells that multi-vector MSI doesn't use global IS
register, nVidia chipsets have different oppinion, requiring every interrupt
to be acknowledged there.
While there, add interrupt descriptions in multi-vector MSI mode.
Change the way in which zero stripesize is handled. Instead of reporting
zero stripeoffset in such case (as if device has no stripes), report offset
from the beginning of the media (as if device has single infinite stripe).
This gives partitioning tools information, required to guess better
partition alignment, in case if hardware doesn't report it's stripe size.
For example, it should give disklabel info about odd offset made by fdisk.
Add a driver for the `Fire' JBus to PCIe bridges found in at least
the Sun Fire V215/V245 and Sun Ultra 25/45 machines. This driver also
already includes all the code to support the `Oberon' Uranus to PCIe
bridges found in the Fujitsu-Siemens based Mx000 machines but due to
lack of access to such a system for testing, probing of these bridges
is currently disabled.
Unfortunately, the event queue mechanism of these bridges for MSIs/
MSI-Xs matches our current MD and MI interrupt frameworks like square
pegs fit into round holes so for now we are generous and use one event
queue per MSI, which limits us to 35 MSIs/MSI-Xs per Host-PCIe-bridge
(we use one event queue for the PCIe error messages). This seems
tolerable as long as most devices just use one MSI/MSI-X anyway.
Adding knowledge about MSIs/MSI-Xs to the MD interrupt code should
allow us to decouple the 1:1 mapping at the cost of no longer being
able to bind MSIs/MSI-Xs to specific CPUs as we currently have no
reliable way to quiesce a device during the transition of its MSIs/
MSI-Xs to another event queue. This would still require the problem
of interrupt storms generated by devices which have no one-shot
behavior or can't/don't mask interrupts while the filter/handler is
executed (like the older PCIe NICs supported by bge(4)) to be solved
though.
- Add code allowing a network device to only be open and closed once
by keeping it opened after the first open and closing it via the
cleanup handler when NETIF_OPEN_CLOSE_ONCE is defined in order to
avoid the open-close-dance on every file access which with firmware
that for example performs an auto-negotiation on every open causes
netbooting to take horribly long. Basically the behavior with this
knob enabled resembles the one employed between r60506 and r177108
(and for sparc64 also again since r182919) with the addition that
the network device now is closed eventually before entering the
kernel and before rebooting. Actually I think this should be the
desired MI behavior, however the U-Boot loader actually requires
net_close() to be called after every transaction in order for some
local shutdown operations to be performed (and which I think thus
will break on concurrent opens, i.e. when netdev_opens is > 1, like
the loader does at least for disks when LOADER_GZIP_SUPPORT is
enabled).
- Use NETIF_OPEN_CLOSE_ONCE to replace the hack, which artificially
increased netdev_opens for sparc64 in order to keep the network
device opened forever, as at least some firmware versions require
the network device to be closed eventually before entering the
kernel or otherwise will DMA received packets to stale memory.
The powerpc OFW loader probably wants NETIF_OPEN_CLOSE_ONCE to be
set as well for the same reasons.
- Demapping unused kernel TLB slots has proven to work reliably so move
the associated debugging under bootverbose.
- Remove freebsd4_sigreturn(); given that FreeBSD 4 didn't supported
sparc64 this only ever served as a transition aid prior to FreeBSD
5.0 and is unused by default since COMPAT_FREEBSD4 was removed from
GENERIC in r143072 nearly 5 years ago.
- Preserve the PROM IOMMU in order to allow OFW drivers to continue to
work.
- Sanity check the parameters passed to the implementations of the
pcib_{read,write}_config() methods. Using illegal values can cause
no real harm but it doesn't hurt to avoid unnecessary data error
traps requiring to flush and re-enable the level 1 caches.
- Prefer i and j over i and n for temporary integer variables.
- Wrap/shorten too long lines.
- Remove a redundant variable and an unnecessary cast in schizo(4).
- Take advantage of bus_{read,write}_*(9).
- Set dow = -1 in mk48txx_gettime() because some drivers (for example
the NetBSD and OpenBSD mk48txx(4)) don't set it correctly.
so requests may bubble up to a host-PCI bridge driver.
- Distinguish between PCI and PCIe bridges in the device description
so it's a bit easier to follow what hangs off of what in the dmesg.
Unfortunately we can't also tell PCI and PCI-X apart based on the
information provided in the OFW device tree.
- Add quirk handling for the ALi M5249 found in Fire-based machines
which are used as a PCIe-PCIe bridge there. These are obviously
subtractive decoding as as they have a PCI-ISA bridge on their
secondary side (and likewise don't include the ISA I/O range in
their bridge decode) but don't indicate this via the class code.
Given that this quirk isn't likely to apply to all ALi M5249 and
I have no datasheet for these chips so I could implement a check
using the chip specific bits enabling subtractive decoding this
quirk handling is added to the MD code rather than the MI one.
Reimplement the boot2 for pc98 completely.
It's based on the newest i386's one and has the advantage of:
- ELF binary support.
- UFS2 filesystem support.
- Many FreeBSD slices support on a disk.
Revert r183628 as with the current ata(4) ATAPI DMA with AcerLabs
M5229 appears to be once again fixed. If this happens to return
we probably should disable ATAPI DMA in ataacerlabs(4) instead
just like the Linux libATA does.
r200950:
Implement RX interrupt moderation using one-shot timer interrupt.
Unlike TX interrupt, ST201 does not provide any mechanism to
suppress RX interrupts. ste(4) can generate more than 70k RX
interrupts under heavy RX traffics such that these excessive
interrupts make system useless to process other useful things.
Maybe this was the major reason why polling support code was
introduced to ste(4).
The STE_COUNTDOWN register provides a programmable counter that
will generate an interrupt upon its expiration. We program
STE_DMACTL register to use 3.2us clock rate to drive the counter
register. Whenever ste(4) serves RX interrupt, the driver rearm
the timer to expire after STE_IM_RX_TIMER_DEFAULT time and disables
further generation of RX interrupts. This trick seems to work well
and ste(4) generates less than 8k RX interrupts even under 64 bytes
UDP torture test. Combined with TX interrupts, the total number of
interrupts are less than 10k which looks reasonable on heavily
loaded controller.
The default RX interrupt moderation time is 150us. Users can change
the value at any time with dev.ste.%d.int_rx_mod sysctl node.
Setting it 0 effectively disables the RX interrupt moderation
feature. Now we have both TX/RX interrupt moderation code so remove
loop of interrupt handler which resulted in sub-optimal performance
as well as more register accesses.
r200955:
Add suspend/resume support as well as basic WOL.
While I'm here simplify SIOCSIFCAP handler.
r200965:
Update if_iqdrops in case of RX buffer allocation failure.
r200966:
ether_ifattach sets if_mtu, remove unnecessary code.
r201767:
Fix EEPROM access code to return data in host byte order.
EEPROM on ST201 always returns 16bits data with little endian
format so conversion to host order is required.
This change fixes inversed ethernet address on sparc64.
r201768:
Make sure to store dma address of RX buffer in little endian form.
This fixes the last bug which keeps ste(4) from working on sparc64.
r200904:
Don't reinitialize controller if driver is already running. This
reduces number of link state UP/DOWN changes.
r200905:
Reimplement controller reset. Datasheet says full reset takes about
1ms. Since we switched to memory register mapping make sure to
flush PCI posted write by reading the register again.
While I'm here add additional delays in loop while driver waits the
completion of the reset.
r200906:
Overhaul RX filter programming.
o Let RX filter handler program promiscuous/multicast filter as
well as broadcasting.
o Remove unnecessary register access.
o Simplify ioctl handler and have set_rxfilter to handle
IFF_PROMISC and IFF_ALLMULTI change instead of directly
programming the controller.
o Removed unnecessary error variable reinitialization in ioctl
handler.
o Add IFF_DRV_RUNNING check before programming multicast filter.
o Configure maximum allowed frame length before enabling MAC.
Datasheet didn't say the exact ordering of programming sequence
but it looks more natural to set maximum allowed frame length
first prior to enabling controller.
r200907:
Don't report link status if driver is not running.
r200908:
Report the correct result of mii_mediachg(). Previously it always
used to return success without respect to the result.
While I'm here use mii_mediachg() in ste_init_locked which allows
driver to use currently configured media. ste_ifmedia_upd() is
supposed to be called whenever user changes current media settings.
r200910:
Implement hardware MAC statistics counter support. The counters
could be accessed with dev.ste.0.stats sysctl node.
r200911:
Remove unused duplicated register definition. It seems the
definition was made to access STE_ASICCTL register as 16bits but
ste(4) always access the register as 32bits so it was never used
before.
r200912:
Correct STE_COUNTDOWN register offset. The datasheet was wrong.
r200913:
We don't need to generate DMA complete interrupt for every
transmitted frames. So request interrupt for every 16th frames. Due
to the limitation of hardware we can't suppress the interrupt as
driver should have to check TX status register. The TX status
register can store up to 31 TX status so driver can't send more
than 31 frames without reading TX status register.
With this change controller would not generate TX completion
interrupt for every frame, so reclaim transmitted frames in
ste_tick().
r200854:
Add minimal dealy while ste(4) is waiting for the end of active DMA
cycle.
r200856:
Introduce sc_flags member variable and use it to keep track of
link state and PHY related information.
Remove ste_link and ste_one_phy variable of softc as it's not used
anymore.
While I'm here add IFF_DRV_RUNNING check in ste_start_locked().
r200865:
Reimplement miibus_statchg method. Don't rely on link state change
interrupt. If we want to use link state change interrupt ste(4)
should also implement auto-negotiation complete handler as well as
various PHY access handling. Now link state change is handled by
mii(4) polling so it will automatically update link state UP/DOWN
events which in turn make ste(4) usable with lagg(4).
r199559 added a private timer to drive watchdog and the timer also
used to drive MAC statistics update. Because the MAC statistics
update is called whenever statistics counter reaches near-full, it
drove watchdog timer too fast such that it caused false watchdog
timeouts under heavy TX traffic conditions.
Fix the regression by separating ste_stats_update() from driving
watchdog timer and introduce a new function ste_tick() that handles
periodic job such as driving watchdog, MAC statistics update and
link state check etc.
While I'm here clear armed watchdog timer in ste_stop().
r200873:
Instead of relying on hard resetting of controller to stop
receiving incoming traffics, try harder to gracefully stop active
DMA cycles and then stop MACs. This is the way what datasheet
recommends and seems to work reliably. Resetting controller while
active DMAs are in progress is bad thing as we can't predict how
DMAs touche allocated TX/RX buffers. This change ensures controller
stop state before attempting to release allocated TX/RX buffers.
Also update MAC statistics which could have been updated during the
wait time of MAC stop.
While I'm here remove unnecessary controller resets in various
location. ste(4) no longer relies on hard controller reset to stop
controller and resetting controller also clears all configured
settings which makes it hard to implement WOL in near future.
Now resetting a controller is performed in ste_init_locked().
r200875:
Prefer memory space register mapping over io space. If memory space
mapping fails fall back to old io space mapping.
While I'm here use PCIR_BAR macro.
r200877:
Prefer bus_write_{1,2,4}/bus_read_{1,2,4} to
bus_space_write_{1,2,4}/bus_space_read_{1,2,4}.
Remove unused ste_bhandle and ste_btag in softc.
r200884:
Reimplement Tx status error handler as recommended by datasheet.
If ste(4) encounter TX underrun or excessive collisions the TX MAC
of controller is stalled so driver should wake it up again. TX
underrun requires increasing TX threshold value to minimize
further TX underruns. Previously ste(4) used to reset controller
to recover from TX underrun, excessive collision and reclaiming
error. However datasheet says only TX underrun requires resetting
entire controller. So implement ste_restart_tx() that restarts TX
MAC and do not perform full reset except TX underrun case.
Now ste(4) uses CSR_READ_2 instead of CSR_READ_1 to read
STE_TX_STATUS register. This way ste(4) will also read frame id
value and we can write the same value back to STE_TX_FRAMEID
register instead of overwriting it to 0. The datasheet was wrong
in write back of STE_TX_STATUS so add some comments why we do so.
Also always invoke ste_txeoc() after ste_txeof() in ste_poll as
without reading TX status register can stall TX MAC.
Add bus_dma(9) and endianness support to ste(4).
o Sorted includes and added missing header files.
o Added basic endianness support. In theory ste(4) should work on
any architectures.
o Remove the use of contigmalloc(9), contigfree(9) and vtophys(9).
o Added 8 byte alignment limitation of TX/RX descriptor.
o Added 1 byte alignment requirement for TX/RX buffers.
o ste(4) controllers does not support DAC. Limit DMA address space
to be within 32bit address.
o Added spare DMA map to gracefully recover from DMA map failure.
o Removed dead code for checking STE_RXSTAT_DMADONE bit. The bit
was already checked in each iteration of loop so it can't be true.
o Added second argument count to ste_rxeof(). It is used to limit
number of iterations done in RX handler. ATM polling is the only
consumer.
o Removed ste_rxeoc() which was added to address RX stuck issue
(cvs rev 1.66). Unlike TX descriptors, ST201 supports chaining
descriptors to form a ring for RX descriptors. If RX descriptor
chaining is not supported it's possible for controller to stop
receiving incoming frames once controller pass the end of RX
descriptor which in turn requires driver post new RX
descriptors to receive more frames. For TX descriptors which
does not support chaning, we exactly do manual chaining in
driver by concatenating new descriptors to the end of previous
TX chain.
Maybe the workaround was borrowed from other drivers that does
not support RX descriptor chaining, which is not valid for ST201
controllers. I still have no idea how this address RX stuck
issue and I can't reproduce the RX stuck issue on DFE-550TX
controller.
o Removed hw.ste_rxsyncs sysctl as the workaround was removed.
o TX/RX side bus_dmamap_load_mbuf_sg(9) support.
o Reimplemented optimized ste_encap().
o Simplified TX logic of ste_start_locked().
o Added comments for TFD/RFD requirements.
o Increased number of RX descriptors to 128 from 64. 128 gave much
better performance than 64 under high network loads.
