Hans Petter Selasky 21c85d9d3b Multiple fixes and improvements: ... - Put "_LE_" into the register access macros to indicate little endian byte order is expected by the hardware. - Avoid using the bounce buffer when not strictly needed. Try to move data directly using bus-space functions first. - Ensure we preserve the reserved bits in the power down mode register. Else the hardware goes into a non-recoverable state. - Always use 32-bit access when writing or reading registers or FIFOs, because the hardware is 32-bit oriented and don't really understand 8- and 16-bit access. - Correct writes to the memory address register. There is no need to shift the register offset. - Correct interval for interrupt endpoints. - Optimise 90ns internal memory buffer read delay. - Rename PDT into PTD, which is how the datasheet writes it. - Add missing programming for activating host controller PTDs. Sponsored by: DARPA, AFRL		2014-05-27 10:01:19 +00:00
..
at91dci.c	- Isochronous transfers should use the alternate next transfer	2014-05-13 13:46:38 +00:00
at91dci.h
at91dci_atmelarm.c	Remove FreeBSD 6 support	2014-02-08 04:29:36 +00:00
at91dci_fdt.c	Add device and gadget bindings for fdt. These are preliminary and will	2014-02-28 03:00:31 +00:00
atmegadci.c	- Isochronous transfers should use the alternate next transfer	2014-05-13 13:46:38 +00:00
atmegadci.h
atmegadci_atmelarm.c
avr32dci.c	- Isochronous transfers should use the alternate next transfer	2014-05-13 13:46:38 +00:00
avr32dci.h
dwc_otg.c	- Add softc pointer argument to FIFO functions as an optimisation.	2014-05-18 09:13:29 +00:00
dwc_otg.h	- Add softc pointer argument to FIFO functions as an optimisation.	2014-05-18 09:13:29 +00:00
dwc_otg_fdt.c	- Add softc pointer argument to FIFO functions as an optimisation.	2014-05-18 09:13:29 +00:00
dwc_otgreg.h	Multiple DWC OTG host mode related fixes and improvements:	2014-05-09 14:23:06 +00:00
ehci.c	Issue doorbell twice before finally freeing the DMA descriptors. This	2014-02-12 08:04:38 +00:00
ehci.h
ehci_fsl.c
ehci_imx.c	Stop calling imx51_ccm_foo() clock functions from imx6 code. Instead	2014-04-26 16:48:09 +00:00
ehci_ixp4xx.c
ehci_mv.c
ehci_pci.c
ehcireg.h
musb_otg.c	- Isochronous transfers should use the alternate next transfer	2014-05-13 13:46:38 +00:00
musb_otg.h
musb_otg_atmelarm.c
ohci.c
ohci.h
ohci_atmelarm.c	Remove FreeBSD 6 support	2014-02-08 04:29:36 +00:00
ohci_fdt.c	Add device and gadget bindings for fdt. These are preliminary and will	2014-02-28 03:00:31 +00:00
ohci_pci.c
ohci_s3c24x0.c
ohcireg.h
saf1761_otg.c	Multiple fixes and improvements:	2014-05-27 10:01:19 +00:00
saf1761_otg.h	Multiple fixes and improvements:	2014-05-27 10:01:19 +00:00
saf1761_otg_fdt.c	Rename "saf1761_dci_xxx" into "saf1761_otg_xxx" to reflect that this	2014-05-16 15:50:21 +00:00
saf1761_otg_reg.h	Multiple fixes and improvements:	2014-05-27 10:01:19 +00:00
uhci.c
uhci.h
uhci_pci.c
uhcireg.h
usb_controller.c	- Add softc pointer argument to FIFO functions as an optimisation.	2014-05-18 09:13:29 +00:00
uss820dci.c	- Isochronous transfers should use the alternate next transfer	2014-05-13 13:46:38 +00:00
uss820dci.h
uss820dci_atmelarm.c
xhci.c	- Fix a bug where the TLBPC value was forced to being odd for IN	2014-05-22 11:58:15 +00:00
xhci.h	Setting the IMOD value below 0x3F8 can cause IRQ lockups in the Intel	2014-04-27 15:41:44 +00:00
xhci_pci.c	Setting the IMOD value below 0x3F8 can cause IRQ lockups in the Intel	2014-04-27 15:41:44 +00:00
xhcireg.h	Setting the IMOD value below 0x3F8 can cause IRQ lockups in the Intel	2014-04-27 15:41:44 +00:00