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a89262079e
Use of compiler builtin ffs/ctz functions will result in optimized instruction sequences when possible, and fall back to calling a function provided by the compiler run-time library. We have slowly shifted our platforms to take advantage of these builtins in60645781d6(arm64),1c76d3a9fb(arm),9e319462a0(powerpc, partial). Some platforms still rely on the libkern implementations of these functions provided by libkern, namely riscv, powerpc (ffs*, flsll), and i386 (ffsll and flsll). These routines are slow, as they perform a linear search for the bit in question. Even on platforms lacking dedicated bit-search instructions, such as riscv, the compiler library will provide better-optimized routines, e.g. by using binary search. Consolidate all definitions of these functions (whether currently using builtins or not) to libkern.h. This should result in equivalent or better performing routines in all cases. One wart in all of this is the existing HAVE_INLINE_F*** macros, which we use in a few places to conditionally avoid the slow libkern routines. These aren't easily removed in one commit. For now, provide these defines unconditionally, but marked for removal after subsequent cleanup. Removal of the now unused libkern routines will follow in the next commit. Reviewed by: dougm, imp (previous version) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D40698
202 lines
5.1 KiB
C
202 lines
5.1 KiB
C
/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
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/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (c) 1997 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Causality Limited.
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* 4. The name of Causality Limited may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* cpufunc.h
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*
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* Prototypes for cpu, mmu and tlb related functions.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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#ifdef _KERNEL
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#include <sys/types.h>
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#include <machine/armreg.h>
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static __inline void
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breakpoint(void)
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{
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__asm("udf 0xffff");
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}
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struct cpu_functions {
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/* CPU functions */
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void (*cf_l2cache_wbinv_all) (void);
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void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
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void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
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void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
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void (*cf_l2cache_drain_writebuf) (void);
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/* Other functions */
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void (*cf_sleep) (int mode);
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void (*cf_setup) (void);
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};
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extern struct cpu_functions cpufuncs;
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extern u_int cputype;
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#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
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#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
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#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
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#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
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#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
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#define cpu_sleep(m) cpufuncs.cf_sleep(m)
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#define cpu_setup() cpufuncs.cf_setup()
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int set_cpufuncs (void);
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#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
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void cpufunc_nullop (void);
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u_int cpufunc_control (u_int clear, u_int bic);
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#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
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void armv7_cpu_sleep (int);
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#endif
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#if defined(CPU_MV_PJ4B)
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void pj4b_config (void);
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#endif
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#if defined(CPU_ARM1176)
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void arm11x6_sleep (int); /* no ref. for errata */
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#endif
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/*
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* Macros for manipulating CPU interrupts
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*/
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#define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A)
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static __inline uint32_t
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__set_cpsr(uint32_t bic, uint32_t eor)
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{
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uint32_t tmp, ret;
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__asm __volatile(
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"mrs %0, cpsr\n" /* Get the CPSR */
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"bic %1, %0, %2\n" /* Clear bits */
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"eor %1, %1, %3\n" /* XOR bits */
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"msr cpsr_xc, %1\n" /* Set the CPSR */
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: "=&r" (ret), "=&r" (tmp)
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: "r" (bic), "r" (eor) : "memory");
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return ret;
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}
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static __inline uint32_t
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disable_interrupts(uint32_t mask)
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{
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return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS));
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}
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static __inline uint32_t
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enable_interrupts(uint32_t mask)
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{
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return (__set_cpsr(mask & __ARM_INTR_BITS, 0));
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}
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static __inline uint32_t
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restore_interrupts(uint32_t old_cpsr)
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{
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return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS));
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}
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static __inline register_t
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intr_disable(void)
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{
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return (disable_interrupts(PSR_I | PSR_F));
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}
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static __inline void
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intr_restore(register_t s)
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{
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restore_interrupts(s);
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}
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#undef __ARM_INTR_BITS
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/*
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* Functions to manipulate cpu r13
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* (in arm/arm32/setstack.S)
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*/
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void set_stackptr (u_int mode, u_int address);
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u_int get_stackptr (u_int mode);
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/*
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* CPU functions from locore.S
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*/
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void cpu_reset (void) __attribute__((__noreturn__));
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/*
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* Cache info variables.
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*/
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/* PRIMARY CACHE VARIABLES */
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extern int arm_dcache_align;
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extern int arm_dcache_align_mask;
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#else /* !_KERNEL */
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static __inline void
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breakpoint(void)
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{
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/*
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* This matches the instruction used by GDB for software
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* breakpoints.
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*/
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__asm("udf 0xfdee");
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}
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#endif /* _KERNEL */
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#endif /* _MACHINE_CPUFUNC_H_ */
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/* End of cpufunc.h */
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