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Here, the provider is responsible for updating the trapframe to redirect control flow and for computing the return address. Once software-saved registers are restored, the emulation shifts the remaining context down on the stack to make space for the return address, then copies the address provided by the invop handler. dtrace_invop() is modified to allocate temporary storage space on the stack for use by the provider to return the return address. This is to support a new provider for amd64 which can instrument arbitrary instructions, not just function entry and exit instructions as FBT does. In collaboration with: christos Sponsored by: Google, Inc. (GSoC 2022) Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
469 lines
10 KiB
ArmAsm
469 lines
10 KiB
ArmAsm
/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License (the "License").
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* You may not use this file except in compliance with the License.
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*
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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* or http://www.opensolaris.org/os/licensing.
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* See the License for the specific language governing permissions
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* and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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*
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* Portions Copyright 2008 John Birrell <jb@freebsd.org>
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*
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* $FreeBSD$
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*
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*/
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/*
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* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
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* Use is subject to license terms.
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*/
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#define _ASM
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#include <machine/asmacros.h>
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#include <sys/cpuvar_defs.h>
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#include <sys/dtrace.h>
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#include "assym.inc"
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#define INTR_POP \
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movq TF_RDI(%rsp),%rdi; \
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movq TF_RSI(%rsp),%rsi; \
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movq TF_RDX(%rsp),%rdx; \
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movq TF_RCX(%rsp),%rcx; \
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movq TF_R8(%rsp),%r8; \
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movq TF_R9(%rsp),%r9; \
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movq TF_RAX(%rsp),%rax; \
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movq TF_RBX(%rsp),%rbx; \
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movq TF_RBP(%rsp),%rbp; \
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movq TF_R10(%rsp),%r10; \
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movq TF_R11(%rsp),%r11; \
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movq TF_R12(%rsp),%r12; \
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movq TF_R13(%rsp),%r13; \
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movq TF_R14(%rsp),%r14; \
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movq TF_R15(%rsp),%r15; \
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testb $SEL_RPL_MASK,TF_CS(%rsp); \
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jz 1f; \
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cli; \
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swapgs; \
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1: addq $TF_RIP,%rsp;
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.globl dtrace_invop_callsite
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.type dtrace_invop_callsite,@function
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ENTRY(dtrace_invop_start)
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/*
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* #BP traps with %rip set to the next address. We need to decrement
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* the value to indicate the address of the int3 (0xcc) instruction
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* that we substituted.
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*/
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movq TF_RIP(%rsp), %rdi
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decq %rdi
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movq %rsp, %rsi
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/*
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* Allocate some scratch space to let the invop handler return a value.
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* This is needed when emulating "call" instructions.
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*/
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subq $16, %rsp
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movq %rsp, %rdx
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call dtrace_invop
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dtrace_invop_callsite:
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addq $16, %rsp
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cmpl $DTRACE_INVOP_PUSHL_EBP, %eax
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je bp_push
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cmpl $DTRACE_INVOP_CALL, %eax
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je bp_call
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cmpl $DTRACE_INVOP_LEAVE, %eax
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je bp_leave
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cmpl $DTRACE_INVOP_NOP, %eax
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je bp_nop
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cmpl $DTRACE_INVOP_RET, %eax
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je bp_ret
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/* When all else fails handle the trap in the usual way. */
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jmpq *dtrace_invop_calltrap_addr
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bp_push:
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/*
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* We must emulate a "pushq %rbp". To do this, we pull the stack
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* down 8 bytes, and then store the base pointer.
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*/
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INTR_POP
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subq $16, %rsp /* make room for %rbp */
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pushq %rax /* push temp */
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movq 24(%rsp), %rax /* load calling RIP */
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movq %rax, 8(%rsp) /* store calling RIP */
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movq 32(%rsp), %rax /* load calling CS */
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movq %rax, 16(%rsp) /* store calling CS */
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movq 40(%rsp), %rax /* load calling RFLAGS */
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movq %rax, 24(%rsp) /* store calling RFLAGS */
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movq 48(%rsp), %rax /* load calling RSP */
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subq $8, %rax /* make room for %rbp */
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movq %rax, 32(%rsp) /* store calling RSP */
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movq 56(%rsp), %rax /* load calling SS */
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movq %rax, 40(%rsp) /* store calling SS */
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movq 32(%rsp), %rax /* reload calling RSP */
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movq %rbp, (%rax) /* store %rbp there */
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popq %rax /* pop off temp */
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iretq /* return from interrupt */
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/*NOTREACHED*/
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bp_call:
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/*
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* Emulate a "call" instruction. The invop handler must have already
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* updated the saved copy of %rip in the register set. It's our job to
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* pull the hardware-saved registers down to make space for the return
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* address, which is provided by the invop handler in our scratch
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* space.
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*/
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INTR_POP
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subq $16, %rsp /* make room for %rbp */
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pushq %rax /* push temp */
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pushq %rbx /* push temp */
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movq 32(%rsp), %rax /* load calling RIP */
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movq %rax, 16(%rsp) /* store calling RIP */
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movq 40(%rsp), %rax /* load calling CS */
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movq %rax, 24(%rsp) /* store calling CS */
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movq 48(%rsp), %rax /* load calling RFLAGS */
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movq %rax, 32(%rsp) /* store calling RFLAGS */
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movq 56(%rsp), %rax /* load calling RSP */
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subq $8, %rax /* make room for return address */
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movq %rax, 40(%rsp) /* store calling RSP */
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movq 64(%rsp), %rax /* load calling SS */
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movq %rax, 48(%rsp) /* store calling SS */
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movq -(TF_RIP - 16)(%rsp), %rax /* load return address */
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movq 40(%rsp), %rbx /* reload calling RSP */
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movq %rax, (%rbx) /* store return address */
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popq %rbx /* pop temp */
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popq %rax /* pop temp */
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iretq /* return from interrupt */
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/*NOTREACHED*/
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bp_leave:
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/*
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* We must emulate a "leave", which is the same as a "movq %rbp, %rsp"
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* followed by a "popq %rbp". This is quite a bit simpler on amd64
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* than it is on i386 -- we can exploit the fact that the %rsp is
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* explicitly saved to effect the pop without having to reshuffle
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* the other data pushed for the trap.
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*/
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INTR_POP
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pushq %rax /* push temp */
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movq 8(%rsp), %rax /* load calling RIP */
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movq %rax, 8(%rsp) /* store calling RIP */
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movq (%rbp), %rax /* get new %rbp */
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addq $8, %rbp /* adjust new %rsp */
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movq %rbp, 32(%rsp) /* store new %rsp */
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movq %rax, %rbp /* set new %rbp */
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popq %rax /* pop off temp */
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iretq /* return from interrupt */
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/*NOTREACHED*/
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bp_nop:
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/* We must emulate a "nop". */
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INTR_POP
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iretq
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/*NOTREACHED*/
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bp_ret:
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INTR_POP
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pushq %rax /* push temp */
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movq 32(%rsp), %rax /* load %rsp */
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movq (%rax), %rax /* load calling RIP */
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movq %rax, 8(%rsp) /* store calling RIP */
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addq $8, 32(%rsp) /* adjust new %rsp */
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popq %rax /* pop off temp */
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iretq /* return from interrupt */
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/*NOTREACHED*/
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END(dtrace_invop_start)
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/*
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greg_t dtrace_getfp(void)
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*/
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ENTRY(dtrace_getfp)
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movq %rbp, %rax
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ret
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END(dtrace_getfp)
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/*
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uint32_t
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dtrace_cas32(uint32_t *target, uint32_t cmp, uint32_t new)
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*/
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ENTRY(dtrace_cas32)
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movl %esi, %eax
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lock
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cmpxchgl %edx, (%rdi)
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ret
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END(dtrace_cas32)
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/*
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void *
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dtrace_casptr(void *target, void *cmp, void *new)
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*/
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ENTRY(dtrace_casptr)
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movq %rsi, %rax
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lock
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cmpxchgq %rdx, (%rdi)
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ret
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END(dtrace_casptr)
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/*
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uintptr_t
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dtrace_caller(int aframes)
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*/
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ENTRY(dtrace_caller)
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movq $-1, %rax
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ret
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END(dtrace_caller)
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/*
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void
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dtrace_copy(uintptr_t src, uintptr_t dest, size_t size)
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*/
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ENTRY(dtrace_copy_nosmap)
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pushq %rbp
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movq %rsp, %rbp
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xchgq %rdi, %rsi /* make %rsi source, %rdi dest */
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movq %rdx, %rcx /* load count */
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repz /* repeat for count ... */
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smovb /* move from %ds:rsi to %ed:rdi */
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leave
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ret
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END(dtrace_copy_nosmap)
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ENTRY(dtrace_copy_smap)
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pushq %rbp
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movq %rsp, %rbp
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xchgq %rdi, %rsi /* make %rsi source, %rdi dest */
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movq %rdx, %rcx /* load count */
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stac
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repz /* repeat for count ... */
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smovb /* move from %ds:rsi to %ed:rdi */
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clac
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leave
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ret
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END(dtrace_copy_smap)
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/*
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void
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dtrace_copystr(uintptr_t uaddr, uintptr_t kaddr, size_t size,
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volatile uint16_t *flags)
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*/
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ENTRY(dtrace_copystr_nosmap)
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pushq %rbp
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movq %rsp, %rbp
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0:
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movb (%rdi), %al /* load from source */
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movb %al, (%rsi) /* store to destination */
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addq $1, %rdi /* increment source pointer */
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addq $1, %rsi /* increment destination pointer */
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subq $1, %rdx /* decrement remaining count */
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cmpb $0, %al
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je 2f
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testq $0xfff, %rdx /* test if count is 4k-aligned */
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jnz 1f /* if not, continue with copying */
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testq $CPU_DTRACE_BADADDR, (%rcx) /* load and test dtrace flags */
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jnz 2f
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1:
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cmpq $0, %rdx
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jne 0b
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2:
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leave
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ret
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END(dtrace_copystr_nosmap)
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ENTRY(dtrace_copystr_smap)
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pushq %rbp
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movq %rsp, %rbp
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stac
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0:
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movb (%rdi), %al /* load from source */
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movb %al, (%rsi) /* store to destination */
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addq $1, %rdi /* increment source pointer */
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addq $1, %rsi /* increment destination pointer */
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subq $1, %rdx /* decrement remaining count */
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cmpb $0, %al
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je 2f
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testq $0xfff, %rdx /* test if count is 4k-aligned */
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jnz 1f /* if not, continue with copying */
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testq $CPU_DTRACE_BADADDR, (%rcx) /* load and test dtrace flags */
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jnz 2f
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1:
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cmpq $0, %rdx
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jne 0b
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2:
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clac
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leave
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ret
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END(dtrace_copystr_smap)
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/*
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uintptr_t
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dtrace_fulword(void *addr)
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*/
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ENTRY(dtrace_fulword_nosmap)
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movq (%rdi), %rax
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ret
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END(dtrace_fulword_nosmap)
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ENTRY(dtrace_fulword_smap)
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stac
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movq (%rdi), %rax
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clac
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ret
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END(dtrace_fulword_smap)
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/*
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uint8_t
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dtrace_fuword8_nocheck(void *addr)
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*/
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ENTRY(dtrace_fuword8_nocheck_nosmap)
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xorq %rax, %rax
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movb (%rdi), %al
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ret
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END(dtrace_fuword8_nocheck_nosmap)
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ENTRY(dtrace_fuword8_nocheck_smap)
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stac
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xorq %rax, %rax
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movb (%rdi), %al
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clac
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ret
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END(dtrace_fuword8_nocheck_smap)
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/*
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uint16_t
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dtrace_fuword16_nocheck(void *addr)
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*/
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ENTRY(dtrace_fuword16_nocheck_nosmap)
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xorq %rax, %rax
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movw (%rdi), %ax
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ret
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END(dtrace_fuword16_nocheck_nosmap)
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ENTRY(dtrace_fuword16_nocheck_smap)
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stac
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xorq %rax, %rax
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movw (%rdi), %ax
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clac
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ret
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END(dtrace_fuword16_nocheck_smap)
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/*
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uint32_t
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dtrace_fuword32_nocheck(void *addr)
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*/
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ENTRY(dtrace_fuword32_nocheck_nosmap)
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xorq %rax, %rax
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movl (%rdi), %eax
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ret
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END(dtrace_fuword32_nocheck_nosmap)
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ENTRY(dtrace_fuword32_nocheck_smap)
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stac
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xorq %rax, %rax
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movl (%rdi), %eax
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clac
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ret
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END(dtrace_fuword32_nocheck_smap)
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/*
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uint64_t
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dtrace_fuword64_nocheck(void *addr)
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*/
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ENTRY(dtrace_fuword64_nocheck_nosmap)
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movq (%rdi), %rax
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ret
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END(dtrace_fuword64_nocheck_nosmap)
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ENTRY(dtrace_fuword64_nocheck_smap)
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stac
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movq (%rdi), %rax
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clac
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ret
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END(dtrace_fuword64_nocheck_smap)
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/*
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void
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dtrace_probe_error(dtrace_state_t *state, dtrace_epid_t epid, int which,
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int fault, int fltoffs, uintptr_t illval)
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*/
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ENTRY(dtrace_probe_error)
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pushq %rbp
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movq %rsp, %rbp
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subq $0x8, %rsp
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movq %r9, (%rsp)
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movq %r8, %r9
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movq %rcx, %r8
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movq %rdx, %rcx
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movq %rsi, %rdx
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movq %rdi, %rsi
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movl dtrace_probeid_error(%rip), %edi
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call dtrace_probe
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addq $0x8, %rsp
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leave
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ret
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END(dtrace_probe_error)
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/*
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void
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dtrace_membar_producer(void)
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*/
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ENTRY(dtrace_membar_producer)
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rep; ret /* use 2 byte return instruction when branch target */
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/* AMD Software Optimization Guide - Section 6.2 */
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END(dtrace_membar_producer)
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/*
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void
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dtrace_membar_consumer(void)
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*/
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ENTRY(dtrace_membar_consumer)
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rep; ret /* use 2 byte return instruction when branch target */
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/* AMD Software Optimization Guide - Section 6.2 */
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END(dtrace_membar_consumer)
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/*
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dtrace_icookie_t
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dtrace_interrupt_disable(void)
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*/
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ENTRY(dtrace_interrupt_disable)
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pushfq
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popq %rax
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cli
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ret
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END(dtrace_interrupt_disable)
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/*
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void
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dtrace_interrupt_enable(dtrace_icookie_t cookie)
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*/
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ENTRY(dtrace_interrupt_enable)
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pushq %rdi
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popfq
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ret
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END(dtrace_interrupt_enable)
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