mirror of
https://github.com/opnsense/src.git
synced 2026-04-02 16:05:17 -04:00
Intel Architecture Manual specifies that rdtsc instruction is not serialized, so without this change, TSC synchronization test would periodically fail, resulting in use of HPET timecounter instead of TSC-low. This caused severe performance degradation (40-50%) when running high IO/s workloads due to HPET MMIO reads and GEOM stat collection. Tests on Xeon E5-2600 (Sandy Bridge) 8C systems were seeing TSC synchronization fail approximately 20% of the time. Sponsored by: Intel Reviewed by: kib MFC after: 3 days |
||
|---|---|---|
| .. | ||
| acpica | ||
| bios | ||
| cpufreq | ||
| include | ||
| isa | ||
| pci | ||
| x86 | ||