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408 lines
13 KiB
C
408 lines
13 KiB
C
/*
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* Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_eeprom_v14.h"
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#include "ar9002/ar9280.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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#include "ar9002/ar9002phy.h"
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#include "ar9002/ar9280_olc.h"
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void
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ar9280olcInit(struct ath_hal *ah)
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{
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uint32_t i;
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/* Only do OLC if it's enabled for this chipset */
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if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))
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return;
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HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Setting up TX gain tables.\n", __func__);
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for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
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AH9280(ah)->originalGain[i] = MS(OS_REG_READ(ah,
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AR_PHY_TX_GAIN_TBL1 + i * 4), AR_PHY_TX_GAIN);
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AH9280(ah)->PDADCdelta = 0;
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}
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void
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ar9280olcGetTxGainIndex(struct ath_hal *ah,
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const struct ieee80211_channel *chan,
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struct calDataPerFreqOpLoop *rawDatasetOpLoop,
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uint8_t *calChans, uint16_t availPiers, uint8_t *pwr, uint8_t *pcdacIdx)
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{
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uint8_t pcdac, i = 0;
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uint16_t idxL = 0, idxR = 0, numPiers;
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HAL_BOOL match;
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CHAN_CENTERS centers;
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ar5416GetChannelCenters(ah, chan, ¢ers);
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for (numPiers = 0; numPiers < availPiers; numPiers++)
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if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
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break;
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match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center,
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IEEE80211_IS_CHAN_2GHZ(chan)), calChans, numPiers,
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&idxL, &idxR);
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if (match) {
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pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
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*pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
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} else {
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pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
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*pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
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rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
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}
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while (pcdac > AH9280(ah)->originalGain[i] &&
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i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
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i++;
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*pcdacIdx = i;
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}
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/*
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* XXX txPower here is likely not the target txPower in the traditional
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* XXX sense, but is set by a call to ar9280olcGetTxGainIndex().
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* XXX Thus, be careful if you're trying to use this routine yourself.
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*/
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void
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ar9280olcGetPDADCs(struct ath_hal *ah, uint32_t initTxGain, int txPower,
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uint8_t *pPDADCValues)
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{
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uint32_t i;
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uint32_t offset;
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OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
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OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
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OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
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offset = txPower;
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for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
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if (i < offset)
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pPDADCValues[i] = 0x0;
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else
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pPDADCValues[i] = 0xFF;
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}
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/*
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* Run temperature compensation calibration.
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*
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* The TX gain table is adjusted depending upon the difference
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* between the initial PDADC value and the currently read
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* average TX power sample value. This value is only valid if
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* frames have been transmitted, so currPDADC will be 0 if
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* no frames have yet been transmitted.
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*/
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void
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ar9280olcTemperatureCompensation(struct ath_hal *ah)
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{
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uint32_t rddata, i;
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int delta, currPDADC, regval;
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uint8_t hpwr_5g = 0;
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if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))
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return;
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rddata = OS_REG_READ(ah, AR_PHY_TX_PWRCTRL4);
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currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
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HALDEBUG(ah, HAL_DEBUG_PERCAL,
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"%s: called: initPDADC=%d, currPDADC=%d\n",
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__func__, AH5416(ah)->initPDADC, currPDADC);
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if (AH5416(ah)->initPDADC == 0 || currPDADC == 0)
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return;
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(void) (ath_hal_eepromGet(ah, AR_EEP_DAC_HPWR_5G, &hpwr_5g));
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if (hpwr_5g)
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delta = (currPDADC - AH5416(ah)->initPDADC + 4) / 8;
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else
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delta = (currPDADC - AH5416(ah)->initPDADC + 5) / 10;
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HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: delta=%d, PDADCdelta=%d\n",
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__func__, delta, AH9280(ah)->PDADCdelta);
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if (delta != AH9280(ah)->PDADCdelta) {
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AH9280(ah)->PDADCdelta = delta;
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for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
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regval = AH9280(ah)->originalGain[i] - delta;
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if (regval < 0)
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regval = 0;
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OS_REG_RMW_FIELD(ah,
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AR_PHY_TX_GAIN_TBL1 + i * 4,
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AR_PHY_TX_GAIN, regval);
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}
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}
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}
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static int16_t
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ar9280ChangeGainBoundarySettings(struct ath_hal *ah, uint16_t *gb,
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uint16_t numXpdGain, uint16_t pdGainOverlap_t2, int8_t pwr_table_offset,
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int16_t *diff)
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{
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uint16_t k;
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/* Prior to writing the boundaries or the pdadc vs. power table
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* into the chip registers the default starting point on the pdadc
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* vs. power table needs to be checked and the curve boundaries
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* adjusted accordingly
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*/
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if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
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uint16_t gb_limit;
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if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
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/* get the difference in dB */
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*diff = (uint16_t)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
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/* get the number of half dB steps */
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*diff *= 2;
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/* change the original gain boundary settings
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* by the number of half dB steps
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*/
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for (k = 0; k < numXpdGain; k++)
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gb[k] = (uint16_t)(gb[k] - *diff);
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}
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/* Because of a hardware limitation, ensure the gain boundary
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* is not larger than (63 - overlap)
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*/
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gb_limit = (uint16_t)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
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for (k = 0; k < numXpdGain; k++)
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gb[k] = (uint16_t)min(gb_limit, gb[k]);
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}
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return *diff;
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}
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static void
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ar9280AdjustPDADCValues(struct ath_hal *ah, int8_t pwr_table_offset,
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int16_t diff, uint8_t *pdadcValues)
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{
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#define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
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uint16_t k;
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/* If this is a board that has a pwrTableOffset that differs from
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* the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
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* pdadc vs pwr table needs to be adjusted prior to writing to the
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* chip.
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*/
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if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
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if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
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/* shift the table to start at the new offset */
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for (k = 0; k < (uint16_t)NUM_PDADC(diff); k++ ) {
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pdadcValues[k] = pdadcValues[k + diff];
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}
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/* fill the back of the table */
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for (k = (uint16_t)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
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pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
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}
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}
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}
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#undef NUM_PDADC
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}
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/*
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* This effectively disables the gain boundaries leaving it
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* to the open-loop TX power control.
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*/
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static void
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ar9280SetGainBoundariesOpenLoop(struct ath_hal *ah, int i,
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uint16_t pdGainOverlap_t2, uint16_t gainBoundaries[])
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{
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int regChainOffset;
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regChainOffset = ar5416GetRegChainOffset(ah, i);
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/* These are unused for OLC */
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(void) pdGainOverlap_t2;
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(void) gainBoundaries;
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HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: chain %d: writing closed loop values\n",
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__func__, i);
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OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
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SM(0x6, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
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SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
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SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
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SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
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SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
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}
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/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */
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/* XXX shouldn't be here! */
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#define EEP_MINOR(_ah) \
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(AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
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#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2)
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#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3)
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/**************************************************************
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* ar9280SetPowerCalTable
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*
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* Pull the PDADC piers from cal data and interpolate them across the given
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* points as well as from the nearest pier(s) to get a power detector
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* linear voltage to power level table.
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*
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* Handle OLC for Merlin where required.
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*/
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HAL_BOOL
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ar9280SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
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const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
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{
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CAL_DATA_PER_FREQ *pRawDataset;
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uint8_t *pCalBChans = AH_NULL;
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uint16_t pdGainOverlap_t2;
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static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
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uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
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uint16_t numPiers, i;
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int16_t tMinCalPower;
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uint16_t numXpdGain, xpdMask;
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uint16_t xpdGainValues[AR5416_NUM_PD_GAINS];
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uint32_t regChainOffset;
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int8_t pwr_table_offset;
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OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));
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xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain;
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(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);
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if (IS_EEP_MINOR_V2(ah)) {
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pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap;
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} else {
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pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
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}
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if (IEEE80211_IS_CHAN_2GHZ(chan)) {
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pCalBChans = pEepData->calFreqPier2G;
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numPiers = AR5416_NUM_2G_CAL_PIERS;
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} else {
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pCalBChans = pEepData->calFreqPier5G;
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numPiers = AR5416_NUM_5G_CAL_PIERS;
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}
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/* If OLC is being done, set the init PDADC value appropriately */
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if (IEEE80211_IS_CHAN_2GHZ(chan) && AR_SREV_MERLIN_20_OR_LATER(ah) &&
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ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
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struct calDataPerFreq *pRawDataset = pEepData->calPierData2G[0];
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AH5416(ah)->initPDADC = ((struct calDataPerFreqOpLoop *) pRawDataset)->vpdPdg[0][0];
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} else {
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/*
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* XXX ath9k doesn't clear this for 5ghz mode if
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* it were set in 2ghz mode before!
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* The Merlin OLC temperature compensation code
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* uses this to calculate the PDADC delta during
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* calibration ; 0 here effectively stops the
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* temperature compensation calibration from
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* occurring.
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*/
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AH5416(ah)->initPDADC = 0;
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}
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/* Calculate the value of xpdgains from the xpdGain Mask */
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numXpdGain = ar5416GetXpdGainValues(ah, xpdMask, xpdGainValues);
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/* Write the detector gain biases and their number */
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ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues);
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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regChainOffset = ar5416GetRegChainOffset(ah, i);
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if (pEepData->baseEepHeader.txMask & (1 << i)) {
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uint16_t diff;
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if (IEEE80211_IS_CHAN_2GHZ(chan)) {
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pRawDataset = pEepData->calPierData2G[i];
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} else {
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pRawDataset = pEepData->calPierData5G[i];
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}
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/* Fetch the gain boundaries and the PDADC values */
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if (AR_SREV_MERLIN_20_OR_LATER(ah) &&
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ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
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uint8_t pcdacIdx;
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uint8_t txPower;
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ar9280olcGetTxGainIndex(ah, chan,
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(struct calDataPerFreqOpLoop *) pRawDataset,
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pCalBChans, numPiers, &txPower, &pcdacIdx);
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ar9280olcGetPDADCs(ah, pcdacIdx, txPower / 2, pdadcValues);
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} else {
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ar5416GetGainBoundariesAndPdadcs(ah, chan,
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pRawDataset, pCalBChans, numPiers,
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pdGainOverlap_t2, &tMinCalPower,
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gainBoundaries, pdadcValues, numXpdGain);
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}
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/*
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* Prior to writing the boundaries or the pdadc vs. power table
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* into the chip registers the default starting point on the pdadc
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* vs. power table needs to be checked and the curve boundaries
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* adjusted accordingly
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*/
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diff = ar9280ChangeGainBoundarySettings(ah,
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gainBoundaries, numXpdGain, pdGainOverlap_t2,
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pwr_table_offset, &diff);
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if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
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/* Set gain boundaries for either open- or closed-loop TPC */
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if (AR_SREV_MERLIN_20_OR_LATER(ah) &&
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ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))
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ar9280SetGainBoundariesOpenLoop(ah,
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i, pdGainOverlap_t2,
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gainBoundaries);
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else
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ar5416SetGainBoundariesClosedLoop(ah,
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i, pdGainOverlap_t2,
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gainBoundaries);
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}
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/*
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* If this is a board that has a pwrTableOffset that differs from
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* the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
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* pdadc vs pwr table needs to be adjusted prior to writing to the
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* chip.
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*/
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ar9280AdjustPDADCValues(ah, pwr_table_offset, diff, pdadcValues);
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/* Write the power values into the baseband power table */
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ar5416WritePdadcValues(ah, i, pdadcValues);
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}
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}
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*pTxPowerIndexOffset = 0;
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return AH_TRUE;
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}
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