mirror of
https://github.com/opnsense/src.git
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50e3b6aa48
Both rwlwifi in Linux and rtwn in OpenBSD restore this register, and the existing code was saving the value and not using it. Reported by: -Wunused-but-set-variable Reviewed by: imp Obtained from: OpenBSD Differential Revision: https://reviews.freebsd.org/D34838
390 lines
11 KiB
C
390 lines
11 KiB
C
/*-
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* Copyright (c) 2017 Kevin Lo <kevlo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_wlan.h"
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#include <sys/param.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/taskqueue.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/linker.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_media.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/rtwn/if_rtwnreg.h>
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#include <dev/rtwn/if_rtwnvar.h>
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#include <dev/rtwn/if_rtwn_debug.h>
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#include <dev/rtwn/rtl8192c/r92c.h>
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#include <dev/rtwn/rtl8192e/r92e.h>
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#include <dev/rtwn/rtl8192e/r92e_reg.h>
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#include <dev/rtwn/rtl8192e/r92e_priv.h>
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#include <dev/rtwn/rtl8192e/r92e_var.h>
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int
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r92e_llt_init(struct rtwn_softc *sc)
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{
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int ntries, error;
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error = rtwn_setbits_4(sc, R92C_AUTO_LLT, 0, R92C_AUTO_LLT_INIT);
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if (error != 0)
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return (error);
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for (ntries = 0; ntries < 1000; ntries++) {
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if (!(rtwn_read_4(sc, R92C_AUTO_LLT) & R92C_AUTO_LLT_INIT))
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return (0);
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rtwn_delay(sc, 1);
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}
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return (ETIMEDOUT);
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}
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static void
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r92e_crystalcap_write(struct rtwn_softc *sc)
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{
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struct r92e_softc *rs = sc->sc_priv;
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uint32_t reg;
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uint8_t val;
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val = rs->crystalcap & 0x3f;
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reg = rtwn_bb_read(sc, R92E_AFE_XTAL_CTRL);
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rtwn_bb_write(sc, R92E_AFE_XTAL_CTRL,
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RW(reg, R92E_AFE_XTAL_CTRL_ADDR, val | val << 6));
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rtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb);
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}
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void
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r92e_init_bb(struct rtwn_softc *sc)
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{
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int i, j;
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rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
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R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD);
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/* Enable BB and RF. */
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rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
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R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
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R92C_SYS_FUNC_EN_DIO_RF);
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/* PathA RF Power On. */
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rtwn_write_1(sc, R92C_RF_CTRL,
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R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
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/* Write BB initialization values. */
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for (i = 0; i < sc->bb_size; i++) {
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const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i];
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while (!rtwn_check_condition(sc, bb_prog->cond)) {
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KASSERT(bb_prog->next != NULL,
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("%s: wrong condition value (i %d)\n",
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__func__, i));
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bb_prog = bb_prog->next;
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}
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for (j = 0; j < bb_prog->count; j++) {
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RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
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"BB: reg 0x%03x, val 0x%08x\n",
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bb_prog->reg[j], bb_prog->val[j]);
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rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);
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rtwn_delay(sc, 1);
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}
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}
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/* Write AGC values. */
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for (i = 0; i < sc->agc_size; i++) {
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const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i];
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while (!rtwn_check_condition(sc, agc_prog->cond)) {
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KASSERT(agc_prog->next != NULL,
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("%s: wrong condition value (2) (i %d)\n",
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__func__, i));
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agc_prog = agc_prog->next;
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}
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for (j = 0; j < agc_prog->count; j++) {
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RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
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"AGC: val 0x%08x\n", agc_prog->val[j]);
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rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
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agc_prog->val[j]);
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rtwn_delay(sc, 1);
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}
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}
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if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR)
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sc->sc_flags |= RTWN_FLAG_CCK_HIPWR;
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rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022);
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rtwn_delay(sc, 1);
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rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020);
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rtwn_delay(sc, 1);
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r92e_crystalcap_write(sc);
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}
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void
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r92e_init_rf(struct rtwn_softc *sc)
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{
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struct r92e_softc *rs = sc->sc_priv;
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uint32_t reg, type;
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int i, chain, idx, off;
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for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) {
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/* Save RF_ENV control type. */
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idx = chain / 2;
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off = (chain % 2) * 16;
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reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
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type = (reg >> off) & 0x10;
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/* Set RF_ENV enable. */
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rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
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0, 0x100000);
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rtwn_delay(sc, 1);
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/* Set RF_ENV output high. */
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rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
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0, 0x10);
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rtwn_delay(sc, 1);
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/* Set address and data lengths of RF registers. */
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rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain),
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R92C_HSSI_PARAM2_ADDR_LENGTH, 0);
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rtwn_delay(sc, 1);
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rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain),
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R92C_HSSI_PARAM2_DATA_LENGTH, 0);
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rtwn_delay(sc, 1);
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/* Write RF initialization values for this chain. */
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i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain);
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/* Restore RF_ENV control type. */
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reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
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reg &= ~(0x10 << off) | (type << off);
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rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
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/* Cache RF register CHNLBW. */
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rs->rf_chnlbw[chain] = rtwn_rf_read(sc, chain, R92C_RF_CHNLBW);
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}
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/* Turn CCK and OFDM blocks on. */
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rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN);
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rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN);
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}
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static void
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r92e_adj_crystal(struct rtwn_softc *sc)
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{
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rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, R92C_AFE_PLL_CTRL_FREF_SEL, 0);
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rtwn_setbits_4(sc, R92E_APE_PLL_CTRL_EXT, 0x00000380, 0);
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rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, 0x40, 0);
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rtwn_setbits_4(sc, R92E_APE_PLL_CTRL_EXT, 0x00200000, 0);
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}
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int
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r92e_power_on(struct rtwn_softc *sc)
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{
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#define RTWN_CHK(res) do { \
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if (res != 0) \
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return (EIO); \
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} while(0)
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int ntries;
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if (rtwn_read_4(sc, R92C_SYS_CFG) & R92C_SYS_CFG_TRP_BT_EN)
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RTWN_CHK(rtwn_write_1(sc, R92C_LDO_SWR_CTRL, 0xc3));
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else {
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RTWN_CHK(rtwn_setbits_4(sc, R92E_LDOV12_CTRL, 0x00100000,
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0x00500000));
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RTWN_CHK(rtwn_write_1(sc, R92C_LDO_SWR_CTRL, 0x83));
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}
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r92e_adj_crystal(sc);
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/* Enable WL suspend. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
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/* Disable HWPDN, SW LPS and WL suspend. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_APFM_RSM | R92C_APS_FSMCO_AFSM_HSUS |
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R92C_APS_FSMCO_AFSM_PCIE | R92C_APS_FSMCO_APDM_HPDN, 0, 1));
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/* Wait for power ready bit. */
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for (ntries = 0; ntries < 5000; ntries++) {
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if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000) {
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device_printf(sc->sc_dev,
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"timeout waiting for chip power up\n");
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return (ETIMEDOUT);
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}
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/* Release WLON reset. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
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R92C_APS_FSMCO_RDY_MACON, 2));
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
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R92C_APS_FSMCO_APFM_ONMAC, 1));
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for (ntries = 0; ntries < 5000; ntries++) {
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if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
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R92C_APS_FSMCO_APFM_ONMAC))
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000)
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return (ETIMEDOUT);
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/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
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RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
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RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
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R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
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R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
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R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
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((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
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R92C_CR_CALTMR_EN));
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return (0);
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}
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void
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r92e_power_off(struct rtwn_softc *sc)
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{
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int error, ntries;
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/* Stop Rx. */
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error = rtwn_write_1(sc, R92C_CR, 0);
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if (error == ENXIO) /* hardware gone */
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return;
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/* Move card to Low Power state. */
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/* Block all Tx queues. */
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rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
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for (ntries = 0; ntries < 5000; ntries++) {
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/* Should be zero if no packet is transmitting. */
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if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000) {
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device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
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__func__);
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return;
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}
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/* CCK and OFDM are disabled, and clock are gated. */
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rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
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rtwn_delay(sc, 1);
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/* Reset whole BB. */
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rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
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/* Reset MAC TRX. */
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rtwn_write_1(sc, R92C_CR,
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R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN);
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/* Check if removed later. */
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rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
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/* Respond TxOK to scheduler */
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rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
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/* Reset MCU. */
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rtwn_write_1(sc, R92C_MCUFWDL, 0);
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#ifndef RTWN_WITHOUT_UCODE
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/* Reset MCU IO wrapper. */
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rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0x01, 0);
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rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
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R92C_SYS_FUNC_EN_CPUEN, 0, 1);
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/* Enable MCU IO wrapper. */
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rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0, 0x01);
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#endif
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/* Move card to Disabled state. */
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/* Turn off RF. */
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rtwn_write_1(sc, R92C_RF_CTRL, 0);
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/* Switch DPDT_SEL_P output. */
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rtwn_setbits_1(sc, R92C_LEDCFG2, 0x80, 0);
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/* Turn off MAC by HW state machine */
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rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
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1);
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for (ntries = 0; ntries < 5000; ntries++) {
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/* Wait until it will be disabled. */
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if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
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R92C_APS_FSMCO_APFM_OFF) == 0)
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000) {
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device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
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__func__);
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return;
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}
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/* SOP option to disable BG/MB. */
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rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
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R92C_APS_FSMCO_SOP_RCK, 3);
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/* Unlock small LDO Register. */
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rtwn_setbits_1(sc, 0xcc, 0, 0x4);
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/* Disable small LDO. */
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rtwn_setbits_1(sc, R92C_SPS0_CTRL, 0x1, 0);
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/* Enable WL suspend. */
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rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE,
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R92C_APS_FSMCO_AFSM_HSUS, 1);
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/* Enable SW LPS. */
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rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
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R92C_APS_FSMCO_APFM_RSM, 1);
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}
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