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Don't use atomic ops to increment interrupt stats. On sparc64 this reduces delay until tick interrupts are service by 1/10th on average. In turn this reduces the clock drift caused by these delays so there's less drift which has to be compensated in tick_hardclock(). This includes switching from atomically incrementing the global cnt.v_intr to the asm equivalent of PCPU_LAZY_INC(cnt.v_intr) in exception.S - Correct some comments to match the registers actually used. - Correct some format specifiers, interrupt levels passed in are u_int. - Use FBSDID. Ok'ed by: jhb |
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| ebus | ||
| fhc | ||
| include | ||
| isa | ||
| pci | ||
| sbus | ||
| sparc64 | ||