Adrian Chadd 9919dec83c if_arge: fix up TX workaround; add TX/RX requirements for busdma; add stats ... The early ethernet MACs (I think AR71xx and AR913x) require that both TX and RX require 4-byte alignment for all packets. The later MACs have started relaxing the requirements. For now, the 1-byte TX and 1-byte RX alignment requirements are only for the QCA955x SoCs. I'll add in the relaxed requirements as I review the datasheets and do testing. * Add a hardware flags field and 1-byte / 4-byte TX/RX alignment. * .. defaulting to 4-byte TX and 4-byte RX alignment. * Only enforce the TX alignment fixup if the hardware requires a 4-byte TX alignment. This avoids a call to m_defrag(). * Add counters for various situations for further debugging. * Set the 1-byte and 4-byte busdma alignment requirement when the tag is created. This improves the straight bridging performance from 130mbit/sec to 180mbit/sec, purely by removing the need for TX path bounce buffers. The main performance issue is the RX alignment requirement and any RX bounce buffering that's occuring. (In a local test, removing the RX fixup path and just aligning buffers raises the performance to above 400mbit/sec. In theory it's a no-op for SoCs before the QCA955x. Tested: * QCA9558 SoC in AP135 board, using software bridging between arge0/arge1.		2015-10-18 00:59:28 +00:00
..
apb.c	ACK interrupts on the new SoCs.	2015-01-05 02:00:41 +00:00
apbvar.h	The AR71xx has APB interrupts in the MISC registers from 0-7, later	2014-03-16 08:39:46 +00:00
ar71xx_bus_space_reversed.c
ar71xx_bus_space_reversed.h
ar71xx_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_chip.h
ar71xx_cpudef.h	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_ehci.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_fixup.c
ar71xx_fixup.h
ar71xx_gpio.c	Add GPIO function mux configuration for AR934x SoCs.	2015-03-21 06:08:35 +00:00
ar71xx_gpiovar.h	Implement GPIO_GET_BUS() method for all GPIO drivers.	2015-01-31 19:32:14 +00:00
ar71xx_macaddr.c	Begin moving support for board MAC addresses over to being explicitly defined.	2015-03-28 23:40:29 +00:00
ar71xx_macaddr.h	Begin moving support for board MAC addresses over to being explicitly defined.	2015-03-28 23:40:29 +00:00
ar71xx_machdep.c	Populate hw.model with the CPU model information.	2015-07-14 05:14:10 +00:00
ar71xx_ohci.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_pci.c	Remove unused variable leading to compile errors.	2015-09-17 06:07:49 +00:00
ar71xx_pci_bus_space.c
ar71xx_pci_bus_space.h
ar71xx_setup.c	Add initial Qualcomm Atheros QCA955x SoC support.	2015-01-05 02:06:26 +00:00
ar71xx_setup.h	add QCA955x SoC types.	2015-01-05 01:59:44 +00:00
ar71xx_spi.c	Devices that rely on hints or identify routines for discovery need to	2013-10-29 14:07:31 +00:00
ar71xx_wdog.c	Devices that rely on hints or identify routines for discovery need to	2013-10-29 14:07:31 +00:00
ar71xxreg.h	Add a MII mode for SGMII.	2015-03-02 01:23:59 +00:00
ar91xx_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar91xx_chip.h
ar91xxreg.h
ar724x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar724x_chip.h
ar724x_pci.c	Remove more unused variables leading to compile time errors.	2015-09-17 12:04:41 +00:00
ar724xreg.h	Note that the AR724x PCIe registers are actually from the PCI_CTRL	2015-03-21 05:59:45 +00:00
ar933x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar933x_chip.h
ar933x_uart.h
ar933xreg.h	Add register definitions for the AR933x SoC GMAC (ie, ethernet MAC)	2013-10-14 23:57:12 +00:00
ar934x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar934x_chip.h	Implement some initial AR934x support routines.	2013-07-21 03:56:57 +00:00
ar934x_nfcreg.h	Add the AR934x NAND flash controller register definitions.	2014-03-18 12:18:35 +00:00
ar934xreg.h	Add AR934x specific GPIO functions and output MUX configuration.	2015-01-03 06:35:53 +00:00
files.ar71xx	Add initial support for the QCA955x PCIe host controller.	2015-05-19 05:31:58 +00:00
if_arge.c	if_arge: fix up TX workaround; add TX/RX requirements for busdma; add stats	2015-10-18 00:59:28 +00:00
if_argevar.h	if_arge: fix up TX workaround; add TX/RX requirements for busdma; add stats	2015-10-18 00:59:28 +00:00
pcf2123_rtc.c
pcf2123reg.h
qca955x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
qca955x_chip.h	Add initial Qualcomm Atheros QCA955x SoC support.	2015-01-05 02:06:26 +00:00
qca955x_pci.c	Remove more unused variables leading to compile time errors.	2015-09-17 12:04:41 +00:00
qca955xreg.h	Oops - fix typo.	2015-07-03 07:00:24 +00:00
std.ar71xx
uart_bus_ar71xx.c	Use the UART frequency when programming the UART clock.	2013-07-21 03:54:39 +00:00
uart_bus_ar933x.c	Use the UART frequency when programming the UART clock.	2013-07-21 03:54:39 +00:00
uart_cpu_ar71xx.c	Use the UART frequency when programming the UART clock.	2013-07-21 03:54:39 +00:00
uart_cpu_ar933x.c	Use the UART frequency when programming the UART clock.	2013-07-21 03:54:39 +00:00
uart_dev_ar933x.c	Add support for the uart classes to set their default register shift value.	2015-04-11 17:16:23 +00:00
uart_dev_ar933x.h