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8a7b91802a
* Support for AlphaStation 200, 250, 255, 400 * Untested support for UDB, Multia, AXPpci33 (Noname) * Support for Personal Workstation 433a/433au, 500a/500au, 600a/600au (Miata) * Some minor fixes and improvements to interrupt handling. Submitted by: Andrew Gallatin <gallatin@cs.duke.edu> (AS200, Miata) Obtained from: NetBSD (some code for AS200, Miata, Noname)
252 lines
6.7 KiB
C
252 lines
6.7 KiB
C
/* $NetBSD: dec_2100_a50.c,v 1.39 1998/04/17 02:45:19 mjacob Exp $ */
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/*
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* Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
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*/
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/*
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* Additional Copyright (c) 1998 by Andrew Gallatin for Duke University
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*/
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/termios.h>
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#include <machine/rpb.h>
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#include <machine/cpuconf.h>
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#include <machine/clock.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <pci/pci_ioctl.h>
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#include <alpha/pci/apecsreg.h>
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#include <alpha/pci/apecsvar.h>
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#include "sio.h"
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#include "sc.h"
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#ifndef CONSPEED
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#define CONSPEED TTYDEF_SPEED
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#endif
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static int comcnrate = CONSPEED;
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void dec_2100_a50_init __P((void));
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static void dec_2100_a50_cons_init __P((void));
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static void dec_2100_a50_device_register __P((struct device *, void *));
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static void dec_2100_a50_intr_map __P((void *));
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void sio_intr_establish __P((int));
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void sio_intr_disestablish __P((int));
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void sio_intr_setup __P((void));
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extern int siocnattach __P((int, int));
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extern int siogdbattach __P((int, int));
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extern int sccnattach __P((void));
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const struct alpha_variation_table dec_2100_a50_variations[] = {
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{ SV_ST_AVANTI, "AlphaStation 400 4/233 (\"Avanti\")" },
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{ SV_ST_MUSTANG2_4_166, "AlphaStation 200 4/166 (\"Mustang II\")" },
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{ SV_ST_MUSTANG2_4_233, "AlphaStation 200 4/233 (\"Mustang II\")" },
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{ SV_ST_AVANTI_4_266, "AlphaStation 250 4/266" },
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{ SV_ST_MUSTANG2_4_100, "AlphaStation 200 4/100 (\"Mustang II\")" },
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{ SV_ST_AVANTI_4_233, "AlphaStation 255/233" },
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{ 0, NULL },
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};
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void
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dec_2100_a50_init()
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{
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u_int64_t variation;
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platform.family = "AlphaStation 200/400 (\"Avanti\")";
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if ((platform.model = alpha_dsr_sysname()) == NULL) {
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variation = hwrpb->rpb_variation & SV_ST_MASK;
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if (variation == SV_ST_AVANTI_XXX) {
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/* XXX apparently the same? */
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variation = SV_ST_AVANTI;
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}
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if ((platform.model = alpha_variation_name(variation,
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dec_2100_a50_variations)) == NULL)
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platform.model = alpha_unknown_sysname();
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}
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platform.iobus = "apecs";
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platform.cons_init = dec_2100_a50_cons_init;
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platform.pci_intr_map = dec_2100_a50_intr_map;
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}
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extern int comconsole; /* XXX for forcing comconsole when srm serial console is used */
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static void
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dec_2100_a50_cons_init()
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{
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struct ctb *ctb;
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apecs_init();
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#ifdef DDB
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siogdbattach(0x2f8, 9600);
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#endif
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ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
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switch (ctb->ctb_term_type) {
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case 2:
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/* serial console ... */
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/* XXX */
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{
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/*
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* Delay to allow PROM putchars to complete.
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* FIFO depth * character time,
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* character time = (1000000 / (defaultrate / 10))
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*/
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DELAY(160000000 / comcnrate);
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/*
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* force a comconsole on com1 if the SRM has a serial console
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*/
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comconsole = 0;
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if (siocnattach(0x3f8, comcnrate))
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panic("can't init serial console");
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break;
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}
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case 3:
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/* display console ... */
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/* XXX */
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#if NSC > 0
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sccnattach();
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#else
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panic("not configured to use display && keyboard console");
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#endif
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break;
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default:
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printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
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printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
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panic("consinit: unknown console type %d\n",
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ctb->ctb_term_type);
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}
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}
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#define SIO_PCIREG_PIRQ_RTCTRL 0x60 /* PIRQ0 Route Control */
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void
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dec_2100_a50_intr_map(void *arg)
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{
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u_int8_t pirqline;
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u_int32_t pirqreg;
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int pirq=0; /* gcc -Wuninitialized XXX */
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pcicfgregs *cfg = (pcicfgregs *)arg;
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static int intr_setup_done=0;
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/*
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* Slot->interrupt translation. Taken from NetBSD
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*/
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if(cfg->intpin == 0)
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return;
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if(cfg->intpin > 4)
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panic("dec_2100_a50_intr_map: bad intpin %d",cfg->intpin);
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switch (cfg->slot) {
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case 6: /* NCR SCSI */
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pirq = 3;
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break;
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case 11: /* slot 1 */
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case 14: /* slot 3 */
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switch(cfg->intpin){
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case 1:
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case 4:
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pirq = 0;
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break;
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case 2:
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pirq = 2;
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break;
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case 3:
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pirq = 1;
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break;
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default:
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panic("dec_2100_a50_intr_map bogus PCI pin %d\n",
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cfg->intpin);
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}
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break;
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case 12: /* slot 2 */
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switch (cfg->intpin) {
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case 1:
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case 4:
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pirq = 1;
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break;
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case 2:
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pirq = 0;
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break;
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case 3:
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pirq = 2;
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break;
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default:
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panic("dec_2100_a50_intr_map bogus PCI pin %d\n",
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cfg->intpin);
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};
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break;
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case 13: /* slot 3 */
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switch (cfg->intpin) {
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case 1:
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case 4:
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pirq = 2;
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break;
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case 2:
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pirq = 1;
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break;
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case 3:
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pirq = 0;
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break;
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};
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break;
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default:
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printf("dec_2100_a50_intr_map: weird slot %d\n",
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cfg->slot);
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/* return;*/
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}
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/*
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* read the SIO IRQ routing register to determine where the
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* interrupt will actually be routed. Thank you, NetBSD
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*/
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pirqreg = chipset.cfgreadl(0, 7, 0, SIO_PCIREG_PIRQ_RTCTRL);
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pirqline = (pirqreg >> (pirq * 8)) & 0xff;
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if ((pirqline & 0x80) != 0)
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panic("bad pirqline %d",pirqline);
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pirqline &= 0xf;
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cfg->intline = pirqline;
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}
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