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opnsense-src/sys/dev/tx
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Semen Ustimenko 29563129dd Implemented workaround for EPIC's Application Note 7-15 (concerning 
chip int. and ext. clock synchronisation). Fixed workaround for
transmit threshold underrun. Added volatile keyword to CSR_READ_* and
CSR_WRITE_* macroses. Added DELAYs to eliminate randomness caused
by processor speed. Fixed all TXCON and RXCON registers to be accessed
only when chip is idle, as manual told. Changed epic_init_phy to
drop link by isolating and going loopback, should should force link
partner to restart autonegotiation.

PR: kern/10535,	kern/9742, kern/10575
Submitted by:	Peter Jeremy, David Greenman
1999-03-14 08:30:23 +00:00
..
if_tx.c Implemented workaround for EPIC's Application Note 7-15 (concerning 1999-03-14 08:30:23 +00:00
if_txreg.h Implemented workaround for EPIC's Application Note 7-15 (concerning 1999-03-14 08:30:23 +00:00
if_txvar.h Implemented workaround for EPIC's Application Note 7-15 (concerning 1999-03-14 08:30:23 +00:00