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467 lines
18 KiB
C
467 lines
18 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2002-2007 Neterion, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef XGE_HAL_RING_H
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#define XGE_HAL_RING_H
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#include <dev/nxge/include/xgehal-channel.h>
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#include <dev/nxge/include/xgehal-config.h>
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#include <dev/nxge/include/xgehal-mm.h>
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__EXTERN_BEGIN_DECLS
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/* HW ring configuration */
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#define XGE_HAL_RING_RXDBLOCK_SIZE 0x1000
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#define XGE_HAL_RXD_T_CODE_OK 0x0
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#define XGE_HAL_RXD_T_CODE_PARITY 0x1
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#define XGE_HAL_RXD_T_CODE_ABORT 0x2
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#define XGE_HAL_RXD_T_CODE_PARITY_ABORT 0x3
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#define XGE_HAL_RXD_T_CODE_RDA_FAILURE 0x4
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#define XGE_HAL_RXD_T_CODE_UNKNOWN_PROTO 0x5
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#define XGE_HAL_RXD_T_CODE_BAD_FCS 0x6
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#define XGE_HAL_RXD_T_CODE_BUFF_SIZE 0x7
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#define XGE_HAL_RXD_T_CODE_BAD_ECC 0x8
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#define XGE_HAL_RXD_T_CODE_UNUSED_C 0xC
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#define XGE_HAL_RXD_T_CODE_UNKNOWN 0xF
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#define XGE_HAL_RING_USE_MTU -1
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/* control_1 and control_2 formatting - same for all buffer modes */
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#define XGE_HAL_RXD_GET_L3_CKSUM(control_1) ((u16)(control_1>>16) & 0xFFFF)
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#define XGE_HAL_RXD_GET_L4_CKSUM(control_1) ((u16)(control_1 & 0xFFFF))
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#define XGE_HAL_RXD_MASK_VLAN_TAG vBIT(0xFFFF,48,16)
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#define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val
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#define XGE_HAL_RXD_GET_VLAN_TAG(control_2) ((u16)(control_2 & 0xFFFF))
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#define XGE_HAL_RXD_POSTED_4_XFRAME BIT(7) /* control_1 */
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#define XGE_HAL_RXD_NOT_COMPLETED BIT(0) /* control_2 */
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#define XGE_HAL_RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
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#define XGE_HAL_RXD_GET_T_CODE(control_1) \
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((control_1 & XGE_HAL_RXD_T_CODE)>>48)
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#define XGE_HAL_RXD_SET_T_CODE(control_1, val) \
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(control_1 |= (((u64)val & 0xF) << 48))
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#define XGE_HAL_RXD_MASK_FRAME_TYPE vBIT(0x3,25,2)
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#define XGE_HAL_RXD_MASK_FRAME_PROTO vBIT(0xFFFF,24,8)
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#define XGE_HAL_RXD_GET_FRAME_TYPE(control_1) \
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(u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37))
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#define XGE_HAL_RXD_GET_FRAME_PROTO(control_1) \
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(u8)((control_1 & XGE_HAL_RXD_MASK_FRAME_PROTO) >> 32)
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#define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED BIT(24)
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#define XGE_HAL_RXD_FRAME_PROTO_IPV4 BIT(27)
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#define XGE_HAL_RXD_FRAME_PROTO_IPV6 BIT(28)
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#define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED BIT(29)
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#define XGE_HAL_RXD_FRAME_PROTO_TCP BIT(30)
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#define XGE_HAL_RXD_FRAME_PROTO_UDP BIT(31)
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#define XGE_HAL_RXD_FRAME_TCP_OR_UDP (XGE_HAL_RXD_FRAME_PROTO_TCP | \
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XGE_HAL_RXD_FRAME_PROTO_UDP)
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/**
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* enum xge_hal_frame_type_e - Ethernet frame format.
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* @XGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format.
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* @XGE_HAL_FRAME_TYPE_LLC: LLC format.
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* @XGE_HAL_FRAME_TYPE_SNAP: SNAP format.
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* @XGE_HAL_FRAME_TYPE_IPX: IPX format.
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*
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* Ethernet frame format.
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*/
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typedef enum xge_hal_frame_type_e {
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XGE_HAL_FRAME_TYPE_DIX = 0x0,
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XGE_HAL_FRAME_TYPE_LLC = 0x1,
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XGE_HAL_FRAME_TYPE_SNAP = 0x2,
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XGE_HAL_FRAME_TYPE_IPX = 0x3,
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} xge_hal_frame_type_e;
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/**
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* enum xge_hal_frame_proto_e - Higher-layer ethernet protocols.
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* @XGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN.
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* @XGE_HAL_FRAME_PROTO_IPV4: IPv4.
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* @XGE_HAL_FRAME_PROTO_IPV6: IPv6.
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* @XGE_HAL_FRAME_PROTO_IP_FRAGMENTED: IP fragmented.
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* @XGE_HAL_FRAME_PROTO_TCP: TCP.
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* @XGE_HAL_FRAME_PROTO_UDP: UDP.
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* @XGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP.
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*
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* Higher layer ethernet protocols and options.
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*/
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typedef enum xge_hal_frame_proto_e {
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XGE_HAL_FRAME_PROTO_VLAN_TAGGED = 0x80,
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XGE_HAL_FRAME_PROTO_IPV4 = 0x10,
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XGE_HAL_FRAME_PROTO_IPV6 = 0x08,
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XGE_HAL_FRAME_PROTO_IP_FRAGMENTED = 0x04,
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XGE_HAL_FRAME_PROTO_TCP = 0x02,
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XGE_HAL_FRAME_PROTO_UDP = 0x01,
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XGE_HAL_FRAME_PROTO_TCP_OR_UDP = (XGE_HAL_FRAME_PROTO_TCP | \
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XGE_HAL_FRAME_PROTO_UDP)
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} xge_hal_frame_proto_e;
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/*
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* xge_hal_ring_rxd_1_t
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*/
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typedef struct {
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u64 host_control;
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u64 control_1;
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u64 control_2;
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#define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
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#define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val) vBIT(val,0,16)
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#define XGE_HAL_RXD_1_GET_BUFFER0_SIZE(Control_2) \
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(int)((Control_2 & vBIT(0xFFFF,0,16))>>48)
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#define XGE_HAL_RXD_1_GET_RTH_VALUE(Control_2) \
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(u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16)
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u64 buffer0_ptr;
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} xge_hal_ring_rxd_1_t;
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/*
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* xge_hal_ring_rxd_3_t
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*/
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typedef struct {
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u64 host_control;
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u64 control_1;
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u64 control_2;
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#define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE vBIT(0xFF,8,8)
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#define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val) vBIT(val,8,8)
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#define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
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#define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val) vBIT(val,16,16)
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#define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
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#define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val) vBIT(val,32,16)
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#define XGE_HAL_RXD_3_GET_BUFFER0_SIZE(Control_2) \
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(int)((Control_2 & vBIT(0xFF,8,8))>>48)
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#define XGE_HAL_RXD_3_GET_BUFFER1_SIZE(Control_2) \
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(int)((Control_2 & vBIT(0xFFFF,16,16))>>32)
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#define XGE_HAL_RXD_3_GET_BUFFER2_SIZE(Control_2) \
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(int)((Control_2 & vBIT(0xFFFF,32,16))>>16)
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u64 buffer0_ptr;
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u64 buffer1_ptr;
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u64 buffer2_ptr;
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} xge_hal_ring_rxd_3_t;
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/*
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* xge_hal_ring_rxd_5_t
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*/
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typedef struct {
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#ifdef XGE_OS_HOST_BIG_ENDIAN
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u32 host_control;
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u32 control_3;
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#else
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u32 control_3;
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u32 host_control;
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#endif
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#define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE vBIT(0xFFFF,32,16)
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#define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val) vBIT(val,32,16)
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#define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE vBIT(0xFFFF,48,16)
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#define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val) vBIT(val,48,16)
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#define XGE_HAL_RXD_5_GET_BUFFER3_SIZE(Control_3) \
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(int)((Control_3 & vBIT(0xFFFF,32,16))>>16)
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#define XGE_HAL_RXD_5_GET_BUFFER4_SIZE(Control_3) \
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(int)((Control_3 & vBIT(0xFFFF,48,16)))
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u64 control_1;
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u64 control_2;
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#define XGE_HAL_RXD_5_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
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#define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val) vBIT(val,0,16)
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#define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
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#define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val) vBIT(val,16,16)
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#define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
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#define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val) vBIT(val,32,16)
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#define XGE_HAL_RXD_5_GET_BUFFER0_SIZE(Control_2) \
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(int)((Control_2 & vBIT(0xFFFF,0,16))>>48)
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#define XGE_HAL_RXD_5_GET_BUFFER1_SIZE(Control_2) \
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(int)((Control_2 & vBIT(0xFFFF,16,16))>>32)
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#define XGE_HAL_RXD_5_GET_BUFFER2_SIZE(Control_2) \
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(int)((Control_2 & vBIT(0xFFFF,32,16))>>16)
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u64 buffer0_ptr;
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u64 buffer1_ptr;
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u64 buffer2_ptr;
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u64 buffer3_ptr;
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u64 buffer4_ptr;
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} xge_hal_ring_rxd_5_t;
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#define XGE_HAL_RXD_GET_RTH_SPDM_HIT(Control_1) \
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(u8)((Control_1 & BIT(18))>>45)
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#define XGE_HAL_RXD_GET_RTH_IT_HIT(Control_1) \
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(u8)((Control_1 & BIT(19))>>44)
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#define XGE_HAL_RXD_GET_RTH_HASH_TYPE(Control_1) \
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(u8)((Control_1 & vBIT(0xF,20,4))>>40)
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#define XGE_HAL_RXD_HASH_TYPE_NONE 0x0
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#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV4 0x1
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#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV4 0x2
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#define XGE_HAL_RXD_HASH_TYPE_IPV4 0x3
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#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6 0x4
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#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6 0x5
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#define XGE_HAL_RXD_HASH_TYPE_IPV6 0x6
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#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6_EX 0x7
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#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6_EX 0x8
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#define XGE_HAL_RXD_HASH_TYPE_IPV6_EX 0x9
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typedef u8 xge_hal_ring_block_t[XGE_HAL_RING_RXDBLOCK_SIZE];
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#define XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET 0xFF8
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#define XGE_HAL_RING_MEMBLOCK_IDX_OFFSET 0xFF0
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#define XGE_HAL_RING_RXD_SIZEOF(n) \
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(n==1 ? sizeof(xge_hal_ring_rxd_1_t) : \
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(n==3 ? sizeof(xge_hal_ring_rxd_3_t) : \
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sizeof(xge_hal_ring_rxd_5_t)))
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#define XGE_HAL_RING_RXDS_PER_BLOCK(n) \
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(n==1 ? 127 : (n==3 ? 85 : 63))
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/**
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* struct xge_hal_ring_rxd_priv_t - Receive descriptor HAL-private data.
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* @dma_addr: DMA (mapped) address of _this_ descriptor.
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* @dma_handle: DMA handle used to map the descriptor onto device.
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* @dma_offset: Descriptor's offset in the memory block. HAL allocates
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* descriptors in memory blocks of
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* %XGE_HAL_RING_RXDBLOCK_SIZE
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* bytes. Each memblock is contiguous DMA-able memory. Each
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* memblock contains 1 or more 4KB RxD blocks visible to the
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* Xframe hardware.
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* @dma_object: DMA address and handle of the memory block that contains
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* the descriptor. This member is used only in the "checked"
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* version of the HAL (to enforce certain assertions);
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* otherwise it gets compiled out.
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* @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
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*
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* Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA
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* information associated with the descriptor. Note that ULD can ask HAL
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* to allocate additional per-descriptor space for its own (ULD-specific)
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* purposes.
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*/
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typedef struct xge_hal_ring_rxd_priv_t {
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dma_addr_t dma_addr;
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pci_dma_h dma_handle;
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ptrdiff_t dma_offset;
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#ifdef XGE_DEBUG_ASSERT
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xge_hal_mempool_dma_t *dma_object;
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#endif
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#ifdef XGE_OS_MEMORY_CHECK
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int allocated;
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#endif
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} xge_hal_ring_rxd_priv_t;
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/**
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* struct xge_hal_ring_t - Ring channel.
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* @channel: Channel "base" of this ring, the common part of all HAL
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* channels.
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* @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode,
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* as per Xframe User Guide.
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* @indicate_max_pkts: Maximum number of packets processed within a single
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* interrupt. Can be used to limit the time spent inside hw
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* interrupt.
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* @config: Ring configuration, part of device configuration
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* (see xge_hal_device_config_t{}).
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* @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Xframe spec,
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* 1-buffer mode descriptor is 32 byte long, etc.
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* @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor
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* data (e.g., DMA handle for Solaris)
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* @rxds_per_block: Number of descriptors per hardware-defined RxD
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* block. Depends on the (1-,3-,5-) buffer mode.
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* @mempool: Memory pool, the pool from which descriptors get allocated.
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* (See xge_hal_mm.h).
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* @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal
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* usage. Not to confuse with @rxd_priv_size.
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* @reserved_rxds_arr: Array of RxD pointers. At any point in time each
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* entry in this array is available for allocation
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* (via xge_hal_ring_dtr_reserve()) and posting.
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* @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR.
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* Used in conjunction with @indicate_max_pkts.
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* Ring channel.
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*
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* Note: The structure is cache line aligned to better utilize
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* CPU cache performance.
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*/
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typedef struct xge_hal_ring_t {
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xge_hal_channel_t channel;
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int buffer_mode;
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int indicate_max_pkts;
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xge_hal_ring_config_t *config;
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int rxd_size;
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int rxd_priv_size;
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int rxds_per_block;
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xge_hal_mempool_t *mempool;
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int rxdblock_priv_size;
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void **reserved_rxds_arr;
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int cmpl_cnt;
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} __xge_os_attr_cacheline_aligned xge_hal_ring_t;
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/**
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* struct xge_hal_dtr_info_t - Extended information associated with a
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* completed ring descriptor.
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* @l3_cksum: Result of IP checksum check (by Xframe hardware).
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* This field containing XGE_HAL_L3_CKSUM_OK would mean that
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* the checksum is correct, otherwise - the datagram is
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* corrupted.
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* @l4_cksum: Result of TCP/UDP checksum check (by Xframe hardware).
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* This field containing XGE_HAL_L4_CKSUM_OK would mean that
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* the checksum is correct. Otherwise - the packet is
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* corrupted.
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* @frame: See xge_hal_frame_type_e{}.
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* @proto: Reporting bits for various higher-layer protocols, including (but
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* note restricted to) TCP and UDP. See xge_hal_frame_proto_e{}.
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* @vlan: VLAN tag extracted from the received frame.
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* @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Xframe II
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* hardware if RTH is enabled.
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* @rth_it_hit: Set, If RTH hash value calculated by the Xframe II hardware
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* has a matching entry in the Indirection table.
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* @rth_spdm_hit: Set, If RTH hash value calculated by the Xframe II hardware
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* has a matching entry in the Socket Pair Direct Match table.
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* @rth_hash_type: RTH hash code of the function used to calculate the hash.
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* @reserved_pad: Unused byte.
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*/
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typedef struct xge_hal_dtr_info_t {
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int l3_cksum;
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int l4_cksum;
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int frame; /* zero or more of xge_hal_frame_type_e flags */
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int proto; /* zero or more of xge_hal_frame_proto_e flags */
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int vlan;
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u32 rth_value;
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u8 rth_it_hit;
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u8 rth_spdm_hit;
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u8 rth_hash_type;
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u8 reserved_pad;
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} xge_hal_dtr_info_t;
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/* ========================== RING PRIVATE API ============================ */
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xge_hal_status_e __hal_ring_open(xge_hal_channel_h channelh,
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xge_hal_channel_attr_t *attr);
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void __hal_ring_close(xge_hal_channel_h channelh);
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void __hal_ring_hw_initialize(xge_hal_device_h devh);
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void __hal_ring_mtu_set(xge_hal_device_h devh, int new_mtu);
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void __hal_ring_prc_enable(xge_hal_channel_h channelh);
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void __hal_ring_prc_disable(xge_hal_channel_h channelh);
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xge_hal_status_e __hal_ring_initial_replenish(xge_hal_channel_t *channel,
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xge_hal_channel_reopen_e reopen);
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#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_RING)
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#define __HAL_STATIC_RING
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#define __HAL_INLINE_RING
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__HAL_STATIC_RING __HAL_INLINE_RING int
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__hal_ring_block_memblock_idx(xge_hal_ring_block_t *block);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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__hal_ring_block_memblock_idx_set(xge_hal_ring_block_t*block, int memblock_idx);
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__HAL_STATIC_RING __HAL_INLINE_RING dma_addr_t
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__hal_ring_block_next_pointer(xge_hal_ring_block_t *block);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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__hal_ring_block_next_pointer_set(xge_hal_ring_block_t*block,
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dma_addr_t dma_next);
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__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_ring_rxd_priv_t*
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__hal_ring_rxd_priv(xge_hal_ring_t *ring, xge_hal_dtr_h dtrh);
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/* =========================== RING PUBLIC API ============================ */
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__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e
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xge_hal_ring_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh);
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__HAL_STATIC_RING __HAL_INLINE_RING void*
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xge_hal_ring_dtr_private(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int size);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_info_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
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xge_hal_dtr_info_t *ext_info);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_1b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
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dma_addr_t *dma_pointer, int *pkt_length);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_3b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[],
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int sizes[]);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_3b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
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dma_addr_t dma_pointers[], int sizes[]);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_5b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[],
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int sizes[]);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_5b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
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dma_addr_t dma_pointer[], int sizes[]);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_pre_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_post_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_post_post_wmb(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
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__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e
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xge_hal_ring_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
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u8 *t_code);
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__HAL_STATIC_RING __HAL_INLINE_RING void
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xge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
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__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e
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xge_hal_ring_is_next_dtr_completed(xge_hal_channel_h channelh);
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#else /* XGE_FASTPATH_EXTERN */
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#define __HAL_STATIC_RING static
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#define __HAL_INLINE_RING inline
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#include <dev/nxge/xgehal/xgehal-ring-fp.c>
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#endif /* XGE_FASTPATH_INLINE */
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__EXTERN_END_DECLS
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#endif /* XGE_HAL_RING_H */
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