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0612538e3a
Implement a core clknode driver for the JH7110 (StarFive VisionFive v2) platform. Add clock/reset generator drivers for the PLL, SYS, and AON clock groupings. Co-authored-by: mhorne Reviewed by: mhorne Sponsored by: The FreeBSD Foundation (mhorne's contributions) Differential Revision: https://reviews.freebsd.org/D43037 |
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| .. | ||
| jh7110_clk.c | ||
| jh7110_clk.h | ||
| jh7110_clk_aon.c | ||
| jh7110_clk_pll.c | ||
| jh7110_clk_pll.h | ||
| jh7110_clk_sys.c | ||