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SDM rev. 068 was released yesterday and it contains the description of
the MSR 0x10a IA32_ARCH_CAP. This change adds symbolic definitions for
all bits present in the document, and decode them in the CPU
identification lines printed on boot.
But also, the document defines SSB_NO as bit 4, while FreeBSD used but
2 to detect the need to work-around Speculative Store Bypass
issue. Change code to use the bit from SDM.
Similarly, the document describes bit 3 as an indicator that L1TF
issue is not present, in particular, no L1D flush is needed on
VMENTRY. We used RDCL_NO to avoid flushing, and again I changed the
code to follow new spec from SDM.
In fact my Apollo Lake machine with latest ucode shows this:
IA32_ARCH_CAPS=0x19<RDCL_NO,SKIP_L1DFL_VME,SSB_NO>
Reviewed by: bwidawsk
Sponsored by: The FreeBSD Foundation
MFC after: 3 days
Differential revision: https://reviews.freebsd.org/D18006
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| amd | ||
| intel | ||
| io | ||
| vmm.c | ||
| vmm_dev.c | ||
| vmm_host.c | ||
| vmm_host.h | ||
| vmm_instruction_emul.c | ||
| vmm_ioport.c | ||
| vmm_ioport.h | ||
| vmm_ktr.h | ||
| vmm_lapic.c | ||
| vmm_lapic.h | ||
| vmm_mem.c | ||
| vmm_mem.h | ||
| vmm_stat.c | ||
| vmm_stat.h | ||
| vmm_util.c | ||
| vmm_util.h | ||
| x86.c | ||
| x86.h | ||