Attilio Rao 9af6d512f5 o Relax locking assertions for vm_page_find_least() ... o Relax locking assertions for pmap_enter_object() and add them also to architectures that currently don't have any o Introduce VM_OBJECT_LOCK_DOWNGRADE() which is basically a downgrade operation on the per-object rwlock o Use all the mechanisms above to make vm_map_pmap_enter() to work mostl of the times only with readlocks. Sponsored by: EMC / Isilon storage division Reviewed by: alc		2013-05-21 20:38:19 +00:00
..
clock.c	MFcalloutng:	2013-02-28 13:46:03 +00:00
copyinout.c	Use the ABI-mandated thread pointer register (r2 for ppc32, r13 for ppc64)	2011-06-23 22:21:28 +00:00
interrupt.c	Use the ABI-mandated thread pointer register (r2 for ppc32, r13 for ppc64)	2011-06-23 22:21:28 +00:00
locore.S	1. Have the APs initialize the TLB1 entries from what has been	2012-11-03 22:02:12 +00:00
machdep.c	Switch the vm_object mutex to be a rwlock. This will enable in the	2013-03-09 02:32:23 +00:00
machdep_e500.c	Extract vendor specific Book-E pieces into separate files and have a common	2012-05-30 17:34:40 +00:00
machdep_ppc4xx.c	Extract vendor specific Book-E pieces into separate files and have a common	2012-05-30 17:34:40 +00:00
mp_cpudep.c	Add SMP support on U3-based G5 systems. This does not yet work perfectly:	2009-10-23 03:17:02 +00:00
platform_bare.c	Introduce PLATFORMMETHOD_END and use it.	2013-02-13 02:21:45 +00:00
pmap.c	o Relax locking assertions for vm_page_find_least()	2013-05-21 20:38:19 +00:00
swtch.S	MFppc64:	2010-07-13 05:32:19 +00:00
trap.c	userret() already checks for td_locks when INVARIANTS is enabled, so	2012-09-08 18:27:11 +00:00
trap_subr.S	Fix a typo that resulted in or-ing PTE_UW twice whrn PTE_SW was needed.	2012-07-02 21:21:12 +00:00
vm_machdep.c	For architectures not using direct map , and requiring real KVA page for	2011-01-18 21:57:02 +00:00