Jayachandran C. a541c47546 Do dcache flush on CPU core before enabling threads. ... The dcache flush has to be done using the core control registers before splitting the L1D cache by enabling the hardware threads. Also replace .word calls for mfcr/mtcr with a C macro. In collaboration with: prabhath at netlogicmicro com		2011-11-21 16:43:24 +00:00
..
adm5120	- dump_avail layout should be sequence of [start, end)	2010-12-09 07:47:40 +00:00
alchemy	- dump_avail layout should be sequence of [start, end)	2010-12-09 07:47:40 +00:00
atheros	Close a race where SIOCGIFMEDIA ioctl get inconsistent link status.	2011-10-17 19:49:00 +00:00
cavium	Mark all SYSCTL_NODEs static that have no corresponding SYSCTL_DECLs.	2011-11-07 15:43:11 +00:00
compile
conf	Always leave the -current kernel debugging options on.	2011-11-21 06:45:12 +00:00
idt	Close a race where SIOCGIFMEDIA ioctl get inconsistent link status.	2011-10-17 19:49:00 +00:00
include	XLP processors have the release 2 pagegrain register	2011-11-21 07:55:37 +00:00
malta	The i8259 controller is initialized incorrectly on MALTA. It writes	2011-07-16 00:30:23 +00:00
mips	Fixup cache flush definitions for XLP	2011-11-19 14:14:35 +00:00
nlm	Do dcache flush on CPU core before enabling threads.	2011-11-21 16:43:24 +00:00
rmi	Remove duplicate header includes	2011-06-26 10:07:48 +00:00
rt305x	Import the initial CPU support for the MIPS RALink RT305x SoC.	2011-04-03 14:39:55 +00:00
sentry5	Remove duplicate header includes	2011-06-26 10:07:48 +00:00
sibyte	Remove duplicate header includes	2011-06-26 10:07:48 +00:00