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2e50ba7074
It was written for Nehalem and Westmere, with minor but incomplete updates for Sandy Bridge in78d763a29b. The uncore architecture changed significantly with this generation, bringing new layouts and locations for some MSRs. Misprogramming these MSRs in ucp_start_pmc() may panic the system, and this is trivially reproducible via pmcstat(8) on at least Broadwell and Haswell. Disable the class on these CPUs until it can be updated more completely and leave a TODO comment detailing some of the work required. Note that the nclasses value for Broadwell was already incorrect and doesn't need changing. The result is that any uncore events listed by pmcstat -L will no longer be allocatable, but this is already the case for newer generations of Intel CPUs. PR: 253687 Reported by: Zhenlei Huang <zlei.huang@gmail.com> Reviewed by: kib MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D31389 (cherry picked from commit4f35e8cba2)
361 lines
9.3 KiB
C
361 lines
9.3 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2008 Joseph Koshy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Common code for handling Intel CPUs.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <sys/systm.h>
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#include <machine/cpu.h>
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#include <machine/cputypes.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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static int
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intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
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{
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(void) pc;
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PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
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pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
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/* allow the RDPMC instruction if needed */
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if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
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load_cr4(rcr4() | CR4_PCE);
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PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
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return 0;
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}
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static int
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intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
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{
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(void) pc;
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(void) pp; /* can be NULL */
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PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
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(uintmax_t) rcr4());
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/* always turn off the RDPMC instruction */
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load_cr4(rcr4() & ~CR4_PCE);
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return 0;
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}
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struct pmc_mdep *
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pmc_intel_initialize(void)
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{
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struct pmc_mdep *pmc_mdep;
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enum pmc_cputype cputype;
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int error, family, model, nclasses, ncpus, stepping, verov;
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KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
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("[intel,%d] Initializing non-intel processor", __LINE__));
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PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
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cputype = -1;
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nclasses = 2;
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error = 0;
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verov = 0;
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family = CPUID_TO_FAMILY(cpu_id);
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model = CPUID_TO_MODEL(cpu_id);
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stepping = CPUID_TO_STEPPING(cpu_id);
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snprintf(pmc_cpuid, sizeof(pmc_cpuid), "GenuineIntel-%d-%02X-%X",
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family, model, stepping);
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switch (cpu_id & 0xF00) {
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case 0x600: /* Pentium Pro, Celeron, Pentium II & III */
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switch (model) {
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case 0xE:
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cputype = PMC_CPU_INTEL_CORE;
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break;
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case 0xF:
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/* Per Intel document 315338-020. */
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if (stepping == 0x7) {
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cputype = PMC_CPU_INTEL_CORE;
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verov = 1;
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} else {
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cputype = PMC_CPU_INTEL_CORE2;
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nclasses = 3;
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}
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break;
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case 0x17:
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cputype = PMC_CPU_INTEL_CORE2EXTREME;
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nclasses = 3;
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break;
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case 0x1C: /* Per Intel document 320047-002. */
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cputype = PMC_CPU_INTEL_ATOM;
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nclasses = 3;
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break;
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case 0x1A:
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case 0x1E: /*
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* Per Intel document 253669-032 9/2009,
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* pages A-2 and A-57
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*/
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case 0x1F: /*
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* Per Intel document 253669-032 9/2009,
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* pages A-2 and A-57
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*/
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cputype = PMC_CPU_INTEL_COREI7;
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nclasses = 5;
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break;
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case 0x2E:
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cputype = PMC_CPU_INTEL_NEHALEM_EX;
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nclasses = 3;
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break;
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case 0x25: /* Per Intel document 253669-033US 12/2009. */
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case 0x2C: /* Per Intel document 253669-033US 12/2009. */
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cputype = PMC_CPU_INTEL_WESTMERE;
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nclasses = 5;
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break;
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case 0x2F: /* Westmere-EX, seen in wild */
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cputype = PMC_CPU_INTEL_WESTMERE_EX;
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nclasses = 3;
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break;
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case 0x2A: /* Per Intel document 253669-039US 05/2011. */
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cputype = PMC_CPU_INTEL_SANDYBRIDGE;
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nclasses = 3;
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break;
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case 0x2D: /* Per Intel document 253669-044US 08/2012. */
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cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
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nclasses = 3;
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break;
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case 0x3A: /* Per Intel document 253669-043US 05/2012. */
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cputype = PMC_CPU_INTEL_IVYBRIDGE;
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nclasses = 3;
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break;
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case 0x3E: /* Per Intel document 325462-045US 01/2013. */
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cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
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nclasses = 3;
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break;
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/* Skylake */
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case 0x4e:
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case 0x5e:
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/* Kabylake */
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case 0x8E: /* Per Intel document 325462-063US July 2017. */
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case 0x9E: /* Per Intel document 325462-063US July 2017. */
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cputype = PMC_CPU_INTEL_SKYLAKE;
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nclasses = 3;
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break;
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case 0x55: /* SDM rev 63 */
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cputype = PMC_CPU_INTEL_SKYLAKE_XEON;
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nclasses = 3;
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break;
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case 0x3D:
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case 0x47:
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cputype = PMC_CPU_INTEL_BROADWELL;
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nclasses = 3;
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break;
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case 0x4f:
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case 0x56:
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cputype = PMC_CPU_INTEL_BROADWELL_XEON;
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nclasses = 3;
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break;
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case 0x3F: /* Per Intel document 325462-045US 09/2014. */
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case 0x46: /* Per Intel document 325462-045US 09/2014. */
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/* Should 46 be XEON. probably its own? */
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cputype = PMC_CPU_INTEL_HASWELL_XEON;
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nclasses = 3;
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break;
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case 0x3C: /* Per Intel document 325462-045US 01/2013. */
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case 0x45: /* Per Intel document 325462-045US 09/2014. */
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cputype = PMC_CPU_INTEL_HASWELL;
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nclasses = 3;
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break;
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case 0x37:
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case 0x4A:
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case 0x4D: /* Per Intel document 330061-001 01/2014. */
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case 0x5A:
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case 0x5D:
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cputype = PMC_CPU_INTEL_ATOM_SILVERMONT;
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nclasses = 3;
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break;
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case 0x5C: /* Per Intel document 325462-071US 10/2019. */
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case 0x5F:
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cputype = PMC_CPU_INTEL_ATOM_GOLDMONT;
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nclasses = 3;
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break;
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}
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break;
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}
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if ((int) cputype == -1) {
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printf("pmc: Unknown Intel CPU.\n");
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return (NULL);
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}
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/* Allocate base class and initialize machine dependent struct */
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pmc_mdep = pmc_mdep_alloc(nclasses);
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pmc_mdep->pmd_cputype = cputype;
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pmc_mdep->pmd_switch_in = intel_switch_in;
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pmc_mdep->pmd_switch_out = intel_switch_out;
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ncpus = pmc_cpu_max();
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error = pmc_tsc_initialize(pmc_mdep, ncpus);
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if (error)
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goto error;
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switch (cputype) {
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/*
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* Intel Core, Core 2 and Atom processors.
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*/
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case PMC_CPU_INTEL_ATOM:
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case PMC_CPU_INTEL_ATOM_SILVERMONT:
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case PMC_CPU_INTEL_ATOM_GOLDMONT:
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case PMC_CPU_INTEL_BROADWELL:
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case PMC_CPU_INTEL_BROADWELL_XEON:
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case PMC_CPU_INTEL_SKYLAKE_XEON:
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case PMC_CPU_INTEL_SKYLAKE:
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case PMC_CPU_INTEL_CORE:
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case PMC_CPU_INTEL_CORE2:
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case PMC_CPU_INTEL_CORE2EXTREME:
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_NEHALEM_EX:
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case PMC_CPU_INTEL_IVYBRIDGE:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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case PMC_CPU_INTEL_WESTMERE:
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case PMC_CPU_INTEL_WESTMERE_EX:
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case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
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case PMC_CPU_INTEL_IVYBRIDGE_XEON:
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case PMC_CPU_INTEL_HASWELL:
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case PMC_CPU_INTEL_HASWELL_XEON:
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error = pmc_core_initialize(pmc_mdep, ncpus, verov);
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break;
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default:
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KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
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}
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if (error) {
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pmc_tsc_finalize(pmc_mdep);
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goto error;
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}
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/*
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* Init the uncore class.
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*/
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switch (cputype) {
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/*
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* Intel Corei7 and Westmere processors.
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*/
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_WESTMERE:
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#ifdef notyet
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/*
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* TODO: re-enable uncore class on these processors.
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*
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* The uncore unit was reworked beginning with Sandy Bridge, including
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* the MSRs required to program it. In particular, we need to:
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* - Parse the MSR_UNC_CBO_CONFIG MSR for number of C-box units in the
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* system
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* - Support reading and writing to ARB and C-box units, depending on
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* the requested event
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* - Create some kind of mapping between C-box <--> CPU
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*
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* Also TODO: support other later changes to these interfaces, to
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* enable the uncore class on generations newer than Broadwell.
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* Skylake+ appears to use newer addresses for the uncore MSRs.
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*/
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case PMC_CPU_INTEL_HASWELL:
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case PMC_CPU_INTEL_BROADWELL:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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#endif
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error = pmc_uncore_initialize(pmc_mdep, ncpus);
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break;
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default:
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break;
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}
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error:
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if (error) {
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pmc_mdep_free(pmc_mdep);
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pmc_mdep = NULL;
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}
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return (pmc_mdep);
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}
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void
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pmc_intel_finalize(struct pmc_mdep *md)
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{
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pmc_tsc_finalize(md);
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switch (md->pmd_cputype) {
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case PMC_CPU_INTEL_ATOM:
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case PMC_CPU_INTEL_ATOM_SILVERMONT:
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case PMC_CPU_INTEL_ATOM_GOLDMONT:
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case PMC_CPU_INTEL_BROADWELL:
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case PMC_CPU_INTEL_BROADWELL_XEON:
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case PMC_CPU_INTEL_SKYLAKE_XEON:
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case PMC_CPU_INTEL_SKYLAKE:
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case PMC_CPU_INTEL_CORE:
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case PMC_CPU_INTEL_CORE2:
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case PMC_CPU_INTEL_CORE2EXTREME:
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_NEHALEM_EX:
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case PMC_CPU_INTEL_HASWELL:
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case PMC_CPU_INTEL_HASWELL_XEON:
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case PMC_CPU_INTEL_IVYBRIDGE:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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case PMC_CPU_INTEL_WESTMERE:
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case PMC_CPU_INTEL_WESTMERE_EX:
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case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
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case PMC_CPU_INTEL_IVYBRIDGE_XEON:
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pmc_core_finalize(md);
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break;
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default:
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KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
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}
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/*
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* Uncore.
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*/
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switch (md->pmd_cputype) {
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_WESTMERE:
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#ifdef notyet
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case PMC_CPU_INTEL_HASWELL:
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case PMC_CPU_INTEL_BROADWELL:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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#endif
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pmc_uncore_finalize(md);
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break;
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default:
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break;
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}
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}
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