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opnsense-src/sys/x86
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Olivier Certner 125bbadf60 x86: Add defines for workaround bits in AMD's MSR "Decode Configuration" 
They are a bit more informative than raw hexadecimal values.

While here, sort existing defines of bits for AMD MSRs to match the address
order.

Reviewed by:	kib, emaste
Sponsored by:   The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D41816
2023-09-14 16:24:48 +01:00
..
acpica sys: Remove $FreeBSD$: one-line .c pattern 2023-08-16 11:54:36 -06:00
bios sys: Remove $FreeBSD$: one-line .c pattern 2023-08-16 11:54:36 -06:00
conf sys: Remove $FreeBSD$: one-line sh pattern 2023-08-16 11:54:58 -06:00
cpufreq sys: Remove $FreeBSD$: one-line .c pattern 2023-08-16 11:54:36 -06:00
include x86: Add defines for workaround bits in AMD's MSR "Decode Configuration" 2023-09-14 16:24:48 +01:00
iommu sys: Remove $FreeBSD$: one-line .c pattern 2023-08-16 11:54:36 -06:00
isa sys: Remove $FreeBSD$: one-line .c pattern 2023-08-16 11:54:36 -06:00
linux linux(4): Remove sys/cdefs.h inclusion under x86/linux due to 685dc743 2023-08-18 15:58:32 +03:00
pci sys: Remove $FreeBSD$: one-line .c pattern 2023-08-16 11:54:36 -06:00
x86 x86: Introduce APIC ID limit by default on AMD hardware 2023-08-29 13:25:30 -04:00
xen sys: Remove $FreeBSD$: one-line .c pattern 2023-08-16 11:54:36 -06:00