opnsense-src/sys/riscv
Mitchell Horne cadaabcc72 riscv timer: use stimecmp CSR when available
The Sstc extension defines a new stimecmp CSR, allowing supervisor
software to set the timer, rather than just read it. When supported,
using this avoids the frequent trips through the SBI every time the
CPU's timer expires.

Reviewed by:	jhb
MFC after:	2 weeks
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D40241
2023-05-25 14:07:49 -03:00
..
allwinner aw_wdog: support Allwinner D1 watchdog 2022-04-12 19:51:17 -03:00
conf riscv: Add pass(4) to GENERIC kernel 2023-05-03 05:14:57 +01:00
include riscv: S-mode extension parsing 2023-05-25 14:07:26 -03:00
riscv riscv timer: use stimecmp CSR when available 2023-05-25 14:07:49 -03:00
sifive spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSD 2023-05-12 10:44:03 -06:00