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f785676f2a
all of the features in the current working draft of the upcoming C++ standard, provisionally named C++1y. The code generator's performance is greatly increased, and the loop auto-vectorizer is now enabled at -Os and -O2 in addition to -O3. The PowerPC backend has made several major improvements to code generation quality and compile time, and the X86, SPARC, ARM32, Aarch64 and SystemZ backends have all seen major feature work. Release notes for llvm and clang can be found here: <http://llvm.org/releases/3.4/docs/ReleaseNotes.html> <http://llvm.org/releases/3.4/tools/clang/docs/ReleaseNotes.html> MFC after: 1 month
104 lines
3.4 KiB
C++
104 lines
3.4 KiB
C++
//===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMHazardRecognizer.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
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const TargetRegisterInfo &TRI) {
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// FIXME: Detect integer instructions properly.
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const MCInstrDesc &MCID = MI->getDesc();
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unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
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if (MI->mayStore())
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return false;
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unsigned Opcode = MCID.getOpcode();
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if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
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return false;
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if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON))
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return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
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return false;
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}
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ScheduleHazardRecognizer::HazardType
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ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
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MachineInstr *MI = SU->getInstr();
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if (!MI->isDebugValue()) {
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// Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
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// a VMLA / VMLS will cause 4 cycle stall.
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const MCInstrDesc &MCID = MI->getDesc();
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if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
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MachineInstr *DefMI = LastMI;
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const MCInstrDesc &LastMCID = LastMI->getDesc();
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const TargetMachine &TM =
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MI->getParent()->getParent()->getTarget();
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const ARMBaseInstrInfo &TII =
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*static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
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// Skip over one non-VFP / NEON instruction.
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if (!LastMI->isBarrier() &&
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// On A9, AGU and NEON/FPU are muxed.
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!(TII.getSubtarget().isLikeA9() &&
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(LastMI->mayLoad() || LastMI->mayStore())) &&
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(LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
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MachineBasicBlock::iterator I = LastMI;
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if (I != LastMI->getParent()->begin()) {
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I = llvm::prior(I);
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DefMI = &*I;
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}
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}
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if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
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(TII.canCauseFpMLxStall(MI->getOpcode()) ||
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hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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// Try to schedule another instruction for the next 4 cycles.
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if (FpMLxStalls == 0)
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FpMLxStalls = 4;
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return Hazard;
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}
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}
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}
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return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
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}
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void ARMHazardRecognizer::Reset() {
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LastMI = 0;
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FpMLxStalls = 0;
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ScoreboardHazardRecognizer::Reset();
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}
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void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
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MachineInstr *MI = SU->getInstr();
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if (!MI->isDebugValue()) {
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LastMI = MI;
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FpMLxStalls = 0;
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}
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ScoreboardHazardRecognizer::EmitInstruction(SU);
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}
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void ARMHazardRecognizer::AdvanceCycle() {
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if (FpMLxStalls && --FpMLxStalls == 0)
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// Stalled for 4 cycles but still can't schedule any other instructions.
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LastMI = 0;
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ScoreboardHazardRecognizer::AdvanceCycle();
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}
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void ARMHazardRecognizer::RecedeCycle() {
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llvm_unreachable("reverse ARM hazard checking unsupported");
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}
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