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This uses the new layout of the upstream repository, which was recently migrated to GitHub, and converted into a "monorepo". That is, most of the earlier separate sub-projects with their own branches and tags were consolidated into one top-level directory, and are now branched and tagged together. Updating the vendor area to match this layout is next.
99 lines
2.5 KiB
C++
99 lines
2.5 KiB
C++
//===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// R600 Machine Scheduler interface
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
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#define LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
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#include "llvm/CodeGen/MachineScheduler.h"
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#include <vector>
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using namespace llvm;
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namespace llvm {
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class R600InstrInfo;
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struct R600RegisterInfo;
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class R600SchedStrategy final : public MachineSchedStrategy {
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const ScheduleDAGMILive *DAG = nullptr;
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const R600InstrInfo *TII = nullptr;
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const R600RegisterInfo *TRI = nullptr;
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MachineRegisterInfo *MRI = nullptr;
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enum InstKind {
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IDAlu,
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IDFetch,
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IDOther,
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IDLast
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};
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enum AluKind {
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AluAny,
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AluT_X,
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AluT_Y,
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AluT_Z,
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AluT_W,
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AluT_XYZW,
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AluPredX,
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AluTrans,
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AluDiscarded, // LLVM Instructions that are going to be eliminated
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AluLast
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};
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std::vector<SUnit *> Available[IDLast], Pending[IDLast];
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std::vector<SUnit *> AvailableAlus[AluLast];
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std::vector<SUnit *> PhysicalRegCopy;
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InstKind CurInstKind;
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int CurEmitted;
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InstKind NextInstKind;
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unsigned AluInstCount;
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unsigned FetchInstCount;
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int InstKindLimit[IDLast];
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int OccupedSlotsMask;
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public:
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R600SchedStrategy() = default;
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~R600SchedStrategy() override = default;
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void initialize(ScheduleDAGMI *dag) override;
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SUnit *pickNode(bool &IsTopNode) override;
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void schedNode(SUnit *SU, bool IsTopNode) override;
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void releaseTopNode(SUnit *SU) override;
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void releaseBottomNode(SUnit *SU) override;
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private:
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std::vector<MachineInstr *> InstructionsGroupCandidate;
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bool VLIW5;
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int getInstKind(SUnit *SU);
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bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
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AluKind getAluKind(SUnit *SU) const;
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void LoadAlu();
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unsigned AvailablesAluCount() const;
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SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
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void PrepareNextSlot();
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SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
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void AssignSlot(MachineInstr *MI, unsigned Slot);
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SUnit* pickAlu();
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SUnit* pickOther(int QID);
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void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
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