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335 lines
9.8 KiB
C
335 lines
9.8 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/haldefs.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/sys.h>
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#include <mips/nlm/hal/nae.h>
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#include <mips/nlm/hal/mdio.h>
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#include <mips/nlm/xlp.h>
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/* Internal MDIO READ/WRITE Routines */
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int
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nlm_int_gmac_mdio_read(uint64_t nae_base, int bus, int block,
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int intf_type, int phyaddr, int regidx)
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{
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uint32_t mdio_ld_cmd;
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uint32_t ctrlval;
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ctrlval = INT_MDIO_CTRL_SMP |
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(phyaddr << INT_MDIO_CTRL_PHYADDR_POS) |
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(regidx << INT_MDIO_CTRL_DEVTYPE_POS) |
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(2 << INT_MDIO_CTRL_OP_POS) |
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(1 << INT_MDIO_CTRL_ST_POS) |
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(7 << INT_MDIO_CTRL_XDIV_POS) |
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(2 << INT_MDIO_CTRL_TA_POS) |
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(2 << INT_MDIO_CTRL_MIIM_POS) |
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(1 << INT_MDIO_CTRL_MCDIV_POS);
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mdio_ld_cmd = nlm_read_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)));
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if (mdio_ld_cmd & INT_MDIO_CTRL_CMD_LOAD) {
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)),
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(mdio_ld_cmd & ~INT_MDIO_CTRL_CMD_LOAD));
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}
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
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ctrlval);
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/* Toggle Load Cmd Bit */
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
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ctrlval | (1 << INT_MDIO_CTRL_LOAD_POS));
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/* poll master busy bit until it is not busy */
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while(nlm_read_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4))) &
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INT_MDIO_STAT_MBSY) {
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}
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
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ctrlval);
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/* Read the data back */
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return nlm_read_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4)));
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}
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/* Internal MDIO WRITE Routines */
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int
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nlm_int_gmac_mdio_write(uint64_t nae_base, int bus, int block,
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int intf_type, int phyaddr, int regidx, uint16_t val)
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{
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uint32_t mdio_ld_cmd;
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uint32_t ctrlval;
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ctrlval = INT_MDIO_CTRL_SMP |
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(phyaddr << INT_MDIO_CTRL_PHYADDR_POS) |
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(regidx << INT_MDIO_CTRL_DEVTYPE_POS) |
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(1 << INT_MDIO_CTRL_OP_POS) |
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(1 << INT_MDIO_CTRL_ST_POS) |
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(7 << INT_MDIO_CTRL_XDIV_POS) |
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(2 << INT_MDIO_CTRL_TA_POS) |
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(1 << INT_MDIO_CTRL_MIIM_POS) |
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(1 << INT_MDIO_CTRL_MCDIV_POS);
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mdio_ld_cmd = nlm_read_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)));
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if (mdio_ld_cmd & INT_MDIO_CTRL_CMD_LOAD) {
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)),
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(mdio_ld_cmd & ~INT_MDIO_CTRL_CMD_LOAD));
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}
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/* load data into ctrl data reg */
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL_DATA + bus * 4)),
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val);
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
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ctrlval);
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
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ctrlval | (1 << INT_MDIO_CTRL_LOAD_POS));
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/* poll master busy bit until it is not busy */
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while(nlm_read_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4))) &
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INT_MDIO_STAT_MBSY) {
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}
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
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ctrlval);
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return (0);
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}
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int
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nlm_int_gmac_mdio_reset(uint64_t nae_base, int bus, int block,
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int intf_type)
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{
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uint32_t val;
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val = (7 << INT_MDIO_CTRL_XDIV_POS) |
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(1 << INT_MDIO_CTRL_MCDIV_POS) |
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(INT_MDIO_CTRL_SMP);
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
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val | INT_MDIO_CTRL_RST);
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
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val);
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return (0);
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}
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/*
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* nae_gmac_mdio_read - Read sgmii phy register
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*
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* Input parameters:
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* bus - bus number, nae has two external gmac bus: 0 and 1
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* phyaddr - PHY's address
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* regidx - index of register to read
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*
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* Return value:
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* value read (16 bits), or 0xffffffff if an error occurred.
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*/
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int
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nlm_gmac_mdio_read(uint64_t nae_base, int bus, int block,
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int intf_type, int phyaddr, int regidx)
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{
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uint32_t mdio_ld_cmd;
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uint32_t ctrlval;
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mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type,
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(EXT_G0_MDIO_CTRL + bus * 4)));
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if (mdio_ld_cmd & EXT_G_MDIO_CMD_LCD) {
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
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(mdio_ld_cmd & ~EXT_G_MDIO_CMD_LCD));
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while(nlm_read_nae_reg(nae_base,
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NAE_REG(block, intf_type,
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(EXT_G0_MDIO_RD_STAT + bus * 4))) &
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EXT_G_MDIO_STAT_MBSY);
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}
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ctrlval = EXT_G_MDIO_CMD_SP |
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(phyaddr << EXT_G_MDIO_PHYADDR_POS) |
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(regidx << EXT_G_MDIO_REGADDR_POS);
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if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax())
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ctrlval |= EXT_G_MDIO_DIV;
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else
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ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64;
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
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ctrlval);
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
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ctrlval | (1<<18));
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DELAY(1000);
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/* poll master busy bit until it is not busy */
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while(nlm_read_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4))) &
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EXT_G_MDIO_STAT_MBSY);
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
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ctrlval);
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/* Read the data back */
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return nlm_read_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4)));
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}
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/*
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* nae_gmac_mdio_write -Write sgmac mii PHY register.
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*
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* Input parameters:
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* bus - bus number, nae has two external gmac bus: 0 and 1
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* phyaddr - PHY to use
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* regidx - register within the PHY
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* val - data to write to register
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*
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* Return value:
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* 0 - success
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*/
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int
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nlm_gmac_mdio_write(uint64_t nae_base, int bus, int block,
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int intf_type, int phyaddr, int regidx, uint16_t val)
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{
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uint32_t mdio_ld_cmd;
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uint32_t ctrlval;
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mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type,
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(EXT_G0_MDIO_CTRL + bus * 4)));
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if (mdio_ld_cmd & EXT_G_MDIO_CMD_LCD) {
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
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(mdio_ld_cmd & ~EXT_G_MDIO_CMD_LCD));
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while(nlm_read_nae_reg(nae_base,
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NAE_REG(block, intf_type,
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(EXT_G0_MDIO_RD_STAT + bus * 4))) &
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EXT_G_MDIO_STAT_MBSY);
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}
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/* load data into ctrl data reg */
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL_DATA+bus*4)),
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val);
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ctrlval = EXT_G_MDIO_CMD_SP |
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(phyaddr << EXT_G_MDIO_PHYADDR_POS) |
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(regidx << EXT_G_MDIO_REGADDR_POS);
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if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax())
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ctrlval |= EXT_G_MDIO_DIV;
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else
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ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64;
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
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ctrlval);
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
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ctrlval | EXT_G_MDIO_CMD_LCD);
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DELAY(1000);
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/* poll master busy bit until it is not busy */
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while(nlm_read_nae_reg(nae_base,
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NAE_REG(block, intf_type,
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(EXT_G0_MDIO_RD_STAT + bus * 4))) & EXT_G_MDIO_STAT_MBSY);
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
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ctrlval);
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return (0);
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}
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/*
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* nae_gmac_mdio_reset -Reset sgmii mdio module.
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*
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* Input parameters:
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* bus - bus number, nae has two external gmac bus: 0 and 1
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*
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* Return value:
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* 0 - success
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*/
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int
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nlm_gmac_mdio_reset(uint64_t nae_base, int bus, int block,
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int intf_type)
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{
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uint32_t ctrlval;
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ctrlval = nlm_read_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)));
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if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax())
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ctrlval |= EXT_G_MDIO_DIV;
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else
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ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64;
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)),
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EXT_G_MDIO_MMRST | ctrlval);
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nlm_write_nae_reg(nae_base,
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NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)), ctrlval);
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return (0);
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}
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/*
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* nlm_mdio_reset_all : reset all internal and external MDIO
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*/
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void
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nlm_mdio_reset_all(uint64_t nae_base)
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{
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/* reset internal MDIO */
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nlm_int_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
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/* reset external MDIO */
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nlm_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
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nlm_gmac_mdio_reset(nae_base, 1, BLOCK_7, LANE_CFG);
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}
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