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Add PCI IDs for Intel Apollo Lake Series HSUARTs:
# pciconf -ll
drv selector class rev hdr vendor device subven subdev
uart0@pci0:0:24:0: 118000 0b 00 8086 5abc 8086 7270
uart1@pci0:0:24:1: 118000 0b 00 8086 5abe 8086 7270
uart2@pci0:0:24:2: 118000 0b 00 8086 5ac0 8086 7270
uart3@pci0:0:24:3: 118000 0b 00 8086 5aee 8086 7270
NB (Intel Document Number 336256-004US):
1. The E3900 and A3900 Series Processors support four LPSS_UART ports,
while the N- and J- Series Processors support only LPSS_UART [2:1]
ports.
2. The LPSS_UART1 port is dedicated for discrete Global Navigation
Satellite System (GNSS). This port can be used for generic UART
functionality if GNSS is not used.
3. The LPSS_UART2 port is dedicated for host OS debug.
4. The LPSS_UART0 and LPSS_UART3 ports are for generic UART functionality.
5. Only UART [1:0] ports support DMA.
PR: 255556
Submitted by: Jose Luis Duran <jlduran@gmail.com>
MFC after: 1 week
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|---|---|---|
| .. | ||
| uart.h | ||
| uart_bus.h | ||
| uart_bus_acpi.c | ||
| uart_bus_fdt.c | ||
| uart_bus_isa.c | ||
| uart_bus_pci.c | ||
| uart_bus_puc.c | ||
| uart_bus_scc.c | ||
| uart_core.c | ||
| uart_cpu.h | ||
| uart_cpu_acpi.c | ||
| uart_cpu_acpi.h | ||
| uart_cpu_arm64.c | ||
| uart_cpu_fdt.c | ||
| uart_cpu_fdt.h | ||
| uart_cpu_powerpc.c | ||
| uart_cpu_x86.c | ||
| uart_dbg.c | ||
| uart_dev_imx.c | ||
| uart_dev_imx.h | ||
| uart_dev_lowrisc.c | ||
| uart_dev_lowrisc.h | ||
| uart_dev_msm.c | ||
| uart_dev_msm.h | ||
| uart_dev_mu.c | ||
| uart_dev_mvebu.c | ||
| uart_dev_ns8250.c | ||
| uart_dev_ns8250.h | ||
| uart_dev_pl011.c | ||
| uart_dev_quicc.c | ||
| uart_dev_snps.c | ||
| uart_dev_ti8250.c | ||
| uart_dev_z8530.c | ||
| uart_if.m | ||
| uart_ppstypes.h | ||
| uart_subr.c | ||
| uart_tty.c | ||