Conrad Meyer 2744a0b69b Drop CACHE_LINE_SIZE to 64 bytes on x86 ... The actual cache line size has always been 64 bytes. The 128 number arose as an optimization for Core 2 era Intel processors. By default (configurable in BIOS), these CPUs would prefetch adjacent cache lines unintelligently. Newer CPUs prefetch more intelligently. The latest Core 2 era CPU was introduced in September 2008 (Xeon 7400 series, "Dunnington"). If you are still using one of these CPUs, especially in a multi-socket configuration, consider locating the "adjacent cache line prefetch" option in BIOS and disabling it. Reported by: mjg Reviewed by: np Discussed with: jhb Sponsored by: Dell EMC Isilon		2017-08-28 22:28:41 +00:00
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acpica	Ensure that resume path on amd64 only accesses page tables for normal	2017-05-15 20:52:43 +00:00
amd64	amd64: drop q suffix from rd[fg]sbase for gas compatibility	2017-08-26 23:13:18 +00:00
cloudabi32	Move struct syscall_args syscall arguments parameters container into	2017-06-12 21:03:23 +00:00
cloudabi64	Keep top page on CloudABI to work around AMD Ryzen stability issues.	2017-08-02 13:08:10 +00:00
conf	An MMC/SD/SDIO stack using CAM	2017-07-09 16:57:24 +00:00
ia32	Translate between abridged and full x87 tags for compat32	2017-06-24 11:38:31 +00:00
include	Drop CACHE_LINE_SIZE to 64 bytes on x86	2017-08-28 22:28:41 +00:00
linux	Lower the amd64 shared page, which contains the signal trampoline,	2017-08-02 01:43:35 +00:00
linux32	Avoid using [LINUX_]SHAREDPAGE constant directly in the vdso code.	2017-07-30 21:24:20 +00:00
pci	pcicfg: Fix direct calls of pci_cfg{read,write} on systems w/o PCI host bridge.	2017-05-04 05:28:46 +00:00
sgx	Fix module unload when SGX support is not present in CPU.	2017-08-18 14:47:06 +00:00
vmm	Save KGSBASE in pcb before overriding it with the guest value.	2017-08-24 10:49:53 +00:00
Makefile	Bring the tags and links entries for amd64 up to date.	2015-10-27 22:59:24 +00:00