mirror of
https://github.com/opnsense/src.git
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26bf8fff64
Sponsored by: Beckhoff Automation GmbH & Co. KG (cherry picked from commit 257405d707d77bc55b38e7c2bb83b8a9247a86ae)
251 lines
7.4 KiB
C
251 lines
7.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2023 Beckhoff Automation GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <machine/bus.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/firmware/xilinx/pm_defs.h>
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#include "hwreset_if.h"
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#include "zynqmp_firmware_if.h"
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#define ZYNQMP_RESET_PCIE_CFG 0
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#define ZYNQMP_RESET_PCIE_BRIDGE 1
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#define ZYNQMP_RESET_PCIE_CTRL 2
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#define ZYNQMP_RESET_DP 3
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#define ZYNQMP_RESET_SWDT_CRF 4
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#define ZYNQMP_RESET_AFI_FM5 5
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#define ZYNQMP_RESET_AFI_FM4 6
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#define ZYNQMP_RESET_AFI_FM3 7
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#define ZYNQMP_RESET_AFI_FM2 8
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#define ZYNQMP_RESET_AFI_FM1 9
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#define ZYNQMP_RESET_AFI_FM0 10
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#define ZYNQMP_RESET_GDMA 11
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#define ZYNQMP_RESET_GPU_PP1 12
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#define ZYNQMP_RESET_GPU_PP0 13
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#define ZYNQMP_RESET_GPU 14
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#define ZYNQMP_RESET_GT 15
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#define ZYNQMP_RESET_SATA 16
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#define ZYNQMP_RESET_ACPU3_PWRON 17
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#define ZYNQMP_RESET_ACPU2_PWRON 18
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#define ZYNQMP_RESET_ACPU1_PWRON 19
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#define ZYNQMP_RESET_ACPU0_PWRON 20
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#define ZYNQMP_RESET_APU_L2 21
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#define ZYNQMP_RESET_ACPU3 22
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#define ZYNQMP_RESET_ACPU2 23
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#define ZYNQMP_RESET_ACPU1 24
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#define ZYNQMP_RESET_ACPU0 25
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#define ZYNQMP_RESET_DDR 26
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#define ZYNQMP_RESET_APM_FPD 27
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#define ZYNQMP_RESET_SOFT 28
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#define ZYNQMP_RESET_GEM0 29
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#define ZYNQMP_RESET_GEM1 30
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#define ZYNQMP_RESET_GEM2 31
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#define ZYNQMP_RESET_GEM3 32
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#define ZYNQMP_RESET_QSPI 33
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#define ZYNQMP_RESET_UART0 34
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#define ZYNQMP_RESET_UART1 35
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#define ZYNQMP_RESET_SPI0 36
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#define ZYNQMP_RESET_SPI1 37
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#define ZYNQMP_RESET_SDIO0 38
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#define ZYNQMP_RESET_SDIO1 39
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#define ZYNQMP_RESET_CAN0 40
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#define ZYNQMP_RESET_CAN1 41
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#define ZYNQMP_RESET_I2C0 42
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#define ZYNQMP_RESET_I2C1 43
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#define ZYNQMP_RESET_TTC0 44
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#define ZYNQMP_RESET_TTC1 45
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#define ZYNQMP_RESET_TTC2 46
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#define ZYNQMP_RESET_TTC3 47
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#define ZYNQMP_RESET_SWDT_CRL 48
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#define ZYNQMP_RESET_NAND 49
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#define ZYNQMP_RESET_ADMA 50
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#define ZYNQMP_RESET_GPIO 51
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#define ZYNQMP_RESET_IOU_CC 52
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#define ZYNQMP_RESET_TIMESTAMP 53
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#define ZYNQMP_RESET_RPU_R50 54
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#define ZYNQMP_RESET_RPU_R51 55
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#define ZYNQMP_RESET_RPU_AMBA 56
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#define ZYNQMP_RESET_OCM 57
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#define ZYNQMP_RESET_RPU_PGE 58
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#define ZYNQMP_RESET_USB0_CORERESET 59
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#define ZYNQMP_RESET_USB1_CORERESET 60
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#define ZYNQMP_RESET_USB0_HIBERRESET 61
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#define ZYNQMP_RESET_USB1_HIBERRESET 62
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#define ZYNQMP_RESET_USB0_APB 63
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#define ZYNQMP_RESET_USB1_APB 64
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#define ZYNQMP_RESET_IPI 65
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#define ZYNQMP_RESET_APM_LPD 66
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#define ZYNQMP_RESET_RTC 67
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#define ZYNQMP_RESET_SYSMON 68
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#define ZYNQMP_RESET_AFI_FM6 69
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#define ZYNQMP_RESET_LPD_SWDT 70
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#define ZYNQMP_RESET_FPD 71
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#define ZYNQMP_RESET_RPU_DBG1 72
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#define ZYNQMP_RESET_RPU_DBG0 73
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#define ZYNQMP_RESET_DBG_LPD 74
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#define ZYNQMP_RESET_DBG_FPD 75
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#define ZYNQMP_RESET_APLL 76
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#define ZYNQMP_RESET_DPLL 77
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#define ZYNQMP_RESET_VPLL 78
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#define ZYNQMP_RESET_IOPLL 79
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#define ZYNQMP_RESET_RPLL 80
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#define ZYNQMP_RESET_GPO3_PL_0 81
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#define ZYNQMP_RESET_GPO3_PL_1 82
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#define ZYNQMP_RESET_GPO3_PL_2 83
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#define ZYNQMP_RESET_GPO3_PL_3 84
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#define ZYNQMP_RESET_GPO3_PL_4 85
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#define ZYNQMP_RESET_GPO3_PL_5 86
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#define ZYNQMP_RESET_GPO3_PL_6 87
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#define ZYNQMP_RESET_GPO3_PL_7 88
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#define ZYNQMP_RESET_GPO3_PL_8 89
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#define ZYNQMP_RESET_GPO3_PL_9 90
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#define ZYNQMP_RESET_GPO3_PL_10 91
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#define ZYNQMP_RESET_GPO3_PL_11 92
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#define ZYNQMP_RESET_GPO3_PL_12 93
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#define ZYNQMP_RESET_GPO3_PL_13 94
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#define ZYNQMP_RESET_GPO3_PL_14 95
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#define ZYNQMP_RESET_GPO3_PL_15 96
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#define ZYNQMP_RESET_GPO3_PL_16 97
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#define ZYNQMP_RESET_GPO3_PL_17 98
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#define ZYNQMP_RESET_GPO3_PL_18 99
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#define ZYNQMP_RESET_GPO3_PL_19 100
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#define ZYNQMP_RESET_GPO3_PL_20 101
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#define ZYNQMP_RESET_GPO3_PL_21 102
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#define ZYNQMP_RESET_GPO3_PL_22 103
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#define ZYNQMP_RESET_GPO3_PL_23 104
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#define ZYNQMP_RESET_GPO3_PL_24 105
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#define ZYNQMP_RESET_GPO3_PL_25 106
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#define ZYNQMP_RESET_GPO3_PL_26 107
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#define ZYNQMP_RESET_GPO3_PL_27 108
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#define ZYNQMP_RESET_GPO3_PL_28 109
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#define ZYNQMP_RESET_GPO3_PL_29 110
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#define ZYNQMP_RESET_GPO3_PL_30 111
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#define ZYNQMP_RESET_GPO3_PL_31 112
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#define ZYNQMP_RESET_RPU_LS 113
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#define ZYNQMP_RESET_PS_ONLY 114
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#define ZYNQMP_RESET_PL 115
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#define ZYNQMP_RESET_PS_PL0 116
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#define ZYNQMP_RESET_PS_PL1 117
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#define ZYNQMP_RESET_PS_PL2 118
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#define ZYNQMP_RESET_PS_PL3 119
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#define ZYNQMP_RESET_MAX ZYNQMP_RESET_PS_PL3
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struct zynqmp_reset_softc {
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device_t dev;
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device_t parent;
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};
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static int
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zynqmp_reset_assert(device_t dev, intptr_t id, bool reset)
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{
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struct zynqmp_reset_softc *sc;
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int rv;
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if (id > ZYNQMP_RESET_MAX)
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return (EINVAL);
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sc = device_get_softc(dev);
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rv = ZYNQMP_FIRMWARE_RESET_ASSERT(sc->parent, id, reset);
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return (rv);
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}
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static int
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zynqmp_reset_is_asserted(device_t dev, intptr_t id, bool *reset)
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{
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struct zynqmp_reset_softc *sc;
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int rv;
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if (id > ZYNQMP_RESET_MAX)
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return (EINVAL);
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sc = device_get_softc(dev);
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rv = ZYNQMP_FIRMWARE_RESET_GET_STATUS(sc->parent, id, reset);
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return (rv);
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}
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static int
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zynqmp_reset_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "xlnx,zynqmp-reset"))
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return (ENXIO);
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device_set_desc(dev, "ZynqMP Reset Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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zynqmp_reset_attach(device_t dev)
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{
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struct zynqmp_reset_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->parent = device_get_parent(dev);
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/* register our self as a reset provider */
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hwreset_register_ofw_provider(dev);
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return (0);
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}
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static device_method_t zynqmp_reset_methods[] = {
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/* device_if */
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DEVMETHOD(device_probe, zynqmp_reset_probe),
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DEVMETHOD(device_attach, zynqmp_reset_attach),
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/* Reset interface */
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DEVMETHOD(hwreset_assert, zynqmp_reset_assert),
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DEVMETHOD(hwreset_is_asserted, zynqmp_reset_is_asserted),
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DEVMETHOD_END
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};
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static driver_t zynqmp_reset_driver = {
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"zynqmp_reset",
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zynqmp_reset_methods,
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sizeof(struct zynqmp_reset_softc),
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};
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EARLY_DRIVER_MODULE(zynqmp_reset, simplebus, zynqmp_reset_driver, 0, 0,
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BUS_PASS_BUS + BUS_PASS_ORDER_LAST);
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