mirror of
https://github.com/opnsense/src.git
synced 2026-02-23 18:00:31 -05:00
2bb28b5f8c
Changes since 1.26.6.0 are listed here. This list comes from the Release Notes for "Chelsio Unified Wire 3.17.0.0 for Linux" dated 2022-07-29. Fixes ----- BASE: - Enabled all MA parity interrupt bits. - Use config file value to override number of rx channel. nrxch=1 was not handled in the firmware. - Replaced read only registers with new registers EDC_H_BIST_USER_WDATA0, EDC_H_BIST_USER_WDATA1 and EDC_H_BIST_CMD_LEN to dump the uP memory parity error status registers. - 10G simplex module support enabled. Obtained from: Chelsio Communications MFC after: 1 month Sponsored by: Chelsio Communications |
||
|---|---|---|
| .. | ||
| t4fw-1.27.0.0.bin | ||
| t4fw_cfg.txt | ||
| t4fw_cfg_uwire.txt | ||
| t4fw_interface.h | ||
| t5fw-1.27.0.0.bin | ||
| t5fw_cfg.txt | ||
| t5fw_cfg_fpga.txt | ||
| t5fw_cfg_hashfilter.txt | ||
| t5fw_cfg_uwire.txt | ||
| t6fw-1.27.0.0.bin | ||
| t6fw_cfg.txt | ||
| t6fw_cfg_fpga.txt | ||
| t6fw_cfg_hashfilter.txt | ||
| t6fw_cfg_uwire.txt | ||