Alan Cox 1bef4955bc On a context switch, handle the possibility that the old thread was ... preempted after an "ic" or "tlbi" instruction but before it performed a "dsb" instruction. The "ic" and "tlbi" instructions have unusual synchronization requirements. If the old thread migrates to a new processor, its completion of a "dsb" instruction on that new processor does not guarantee that the "ic" or "tlbi" instructions performed on the old processor have completed. This issue is not restricted to the kernel. Since locore.S sets the UCI bit in SCTLR, user-space programs can perform "ic ivau" instructions (as well as some forms of the "dc" instruction). Reviewed by: andrew, kib, markj, mmel X-MFC with: r355145 Differential Revision: https://reviews.freebsd.org/D22622		2019-12-05 19:25:49 +00:00
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acpica	arm64 acpi_iort: add some error handling	2019-06-24 21:24:55 +00:00
arm64	On a context switch, handle the possibility that the old thread was	2019-12-05 19:25:49 +00:00
cavium	Rename the ThunderX CPU identification macros to include the X. This is the	2018-06-13 12:17:11 +00:00
cloudabi32	Use uintptr_t instead of register_t * for the stack base.	2019-12-03 23:17:54 +00:00
cloudabi64	Use uintptr_t instead of register_t * for the stack base.	2019-12-03 23:17:54 +00:00
conf	Add the I2C driver for the Armada 37x0.	2019-12-05 00:56:03 +00:00
coresight	Extract eventfilter declarations to sys/_eventfilter.h	2019-05-20 00:38:23 +00:00
include	Regularize my copyright notice	2019-12-04 16:56:11 +00:00
intel	Add support for Intel Stratix 10 platform.	2019-09-13 16:50:57 +00:00
linux	Fix arm64 build after r355373	2019-12-04 08:21:54 +00:00
qualcomm	Enable Qualcomm Debug Subsystem (QDSS) block on MSM8916 SoC.	2018-04-10 12:53:48 +00:00
rockchip	Remove "all rights reserved" from copyright for the file I own.	2019-12-03 21:00:45 +00:00