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e5592c61ad
Itanium doesn't have the mfence instruction - that's a 386 thing. Use the "mf" instruction instead. This reverts the previous commit to add "#include <emmintrinsic.h>"; the problem was not with a missing #include.
175 lines
6.4 KiB
C
175 lines
6.4 KiB
C
/*-------------------------------------------------------------------------
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*
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* barrier.h
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* Memory barrier operations.
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*
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* Portions Copyright (c) 1996-2013, PostgreSQL Global Development Group
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* Portions Copyright (c) 1994, Regents of the University of California
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*
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* src/include/storage/barrier.h
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*
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*-------------------------------------------------------------------------
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*/
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#ifndef BARRIER_H
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#define BARRIER_H
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#include "storage/s_lock.h"
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extern slock_t dummy_spinlock;
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/*
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* A compiler barrier need not (and preferably should not) emit any actual
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* machine code, but must act as an optimization fence: the compiler must not
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* reorder loads or stores to main memory around the barrier. However, the
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* CPU may still reorder loads or stores at runtime, if the architecture's
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* memory model permits this.
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*
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* A memory barrier must act as a compiler barrier, and in addition must
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* guarantee that all loads and stores issued prior to the barrier are
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* completed before any loads or stores issued after the barrier. Unless
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* loads and stores are totally ordered (which is not the case on most
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* architectures) this requires issuing some sort of memory fencing
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* instruction.
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*
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* A read barrier must act as a compiler barrier, and in addition must
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* guarantee that any loads issued prior to the barrier are completed before
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* any loads issued after the barrier. Similarly, a write barrier acts
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* as a compiler barrier, and also orders stores. Read and write barriers
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* are thus weaker than a full memory barrier, but stronger than a compiler
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* barrier. In practice, on machines with strong memory ordering, read and
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* write barriers may require nothing more than a compiler barrier.
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*
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* For an introduction to using memory barriers within the PostgreSQL backend,
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* see src/backend/storage/lmgr/README.barrier
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*/
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#if defined(DISABLE_BARRIERS)
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/*
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* Fall through to the spinlock-based implementation.
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*/
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#elif defined(__INTEL_COMPILER)
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/*
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* icc defines __GNUC__, but doesn't support gcc's inline asm syntax
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*/
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#if defined(__ia64__) || defined(__ia64)
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#define pg_memory_barrier() __mf()
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#else if defined(__i386__) || defined(__x86_64__)
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#define pg_memory_barrier() _mm_mfence()
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#endif
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#define pg_compiler_barrier() __memory_barrier()
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#elif defined(__GNUC__)
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/* This works on any architecture, since it's only talking to GCC itself. */
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#define pg_compiler_barrier() __asm__ __volatile__("" : : : "memory")
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#if defined(__i386__)
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/*
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* i386 does not allow loads to be reordered with other loads, or stores to be
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* reordered with other stores, but a load can be performed before a subsequent
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* store.
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*
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* "lock; addl" has worked for longer than "mfence".
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*/
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#define pg_memory_barrier() \
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__asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory")
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#define pg_read_barrier() pg_compiler_barrier()
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#define pg_write_barrier() pg_compiler_barrier()
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#elif defined(__x86_64__) /* 64 bit x86 */
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/*
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* x86_64 has similar ordering characteristics to i386.
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*
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* Technically, some x86-ish chips support uncached memory access and/or
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* special instructions that are weakly ordered. In those cases we'd need
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* the read and write barriers to be lfence and sfence. But since we don't
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* do those things, a compiler barrier should be enough.
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*/
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#define pg_memory_barrier() \
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__asm__ __volatile__ ("lock; addl $0,0(%%rsp)" : : : "memory")
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#define pg_read_barrier() pg_compiler_barrier()
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#define pg_write_barrier() pg_compiler_barrier()
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#elif defined(__ia64__) || defined(__ia64)
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/*
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* Itanium is weakly ordered, so read and write barriers require a full
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* fence.
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*/
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#define pg_memory_barrier() __asm__ __volatile__ ("mf" : : : "memory")
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#elif defined(__ppc__) || defined(__powerpc__) || defined(__ppc64__) || defined(__powerpc64__)
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/*
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* lwsync orders loads with respect to each other, and similarly with stores.
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* But a load can be performed before a subsequent store, so sync must be used
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* for a full memory barrier.
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*/
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#define pg_memory_barrier() __asm__ __volatile__ ("sync" : : : "memory")
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#define pg_read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
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#define pg_write_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
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#elif defined(__alpha) || defined(__alpha__) /* Alpha */
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/*
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* Unlike all other known architectures, Alpha allows dependent reads to be
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* reordered, but we don't currently find it necessary to provide a conditional
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* read barrier to cover that case. We might need to add that later.
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*/
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#define pg_memory_barrier() __asm__ __volatile__ ("mb" : : : "memory")
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#define pg_read_barrier() __asm__ __volatile__ ("rmb" : : : "memory")
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#define pg_write_barrier() __asm__ __volatile__ ("wmb" : : : "memory")
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#elif __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 1)
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/*
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* If we're on GCC 4.1.0 or higher, we should be able to get a memory
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* barrier out of this compiler built-in. But we prefer to rely on our
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* own definitions where possible, and use this only as a fallback.
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*/
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#define pg_memory_barrier() __sync_synchronize()
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#endif
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#elif defined(__ia64__) || defined(__ia64)
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#define pg_compiler_barrier() _Asm_sched_fence()
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#define pg_memory_barrier() _Asm_mf()
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#elif defined(WIN32_ONLY_COMPILER)
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/* Should work on both MSVC and Borland. */
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#include <intrin.h>
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#pragma intrinsic(_ReadWriteBarrier)
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#define pg_compiler_barrier() _ReadWriteBarrier()
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#define pg_memory_barrier() MemoryBarrier()
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#endif
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/*
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* If we have no memory barrier implementation for this architecture, we
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* fall back to acquiring and releasing a spinlock. This might, in turn,
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* fall back to the semaphore-based spinlock implementation, which will be
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* amazingly slow.
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*
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* It's not self-evident that every possible legal implementation of a
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* spinlock acquire-and-release would be equivalent to a full memory barrier.
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* For example, I'm not sure that Itanium's acq and rel add up to a full
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* fence. But all of our actual implementations seem OK in this regard.
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*/
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#if !defined(pg_memory_barrier)
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#define pg_memory_barrier(x) \
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do { S_LOCK(&dummy_spinlock); S_UNLOCK(&dummy_spinlock); } while (0)
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#endif
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/*
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* If read or write barriers are undefined, we upgrade them to full memory
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* barriers.
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*
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* If a compiler barrier is unavailable, you probably don't want a full
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* memory barrier instead, so if you have a use case for a compiler barrier,
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* you'd better use #ifdef.
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*/
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#if !defined(pg_read_barrier)
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#define pg_read_barrier() pg_memory_barrier()
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#endif
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#if !defined(pg_write_barrier)
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#define pg_write_barrier() pg_memory_barrier()
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#endif
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#endif /* BARRIER_H */
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