David Bright 52e1406947 ntb_hw_intel: fix xeon NTB gen3 bar disable logic ... In NTB gen3 driver, it was supposed to disable NTB bar access by default, but due to incorrect register access method, the bar disable logic does not work as expected. Those registers should be modified through NTB bar0 rather than PCI configuration space. Besides, we'd better to protect ourselves from a bad buddy node so ingress disable logic should be implemented together. Submitted by: Austin Zhang (austin.zhang@dell.com) Sponsored by: Dell EMC (cherry picked from commit e3cf7ebc1d)		2021-10-04 06:53:26 -07:00
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if_ntb	Mark more nodes as CTLFLAG_MPSAFE or CTLFLAG_NEEDGIANT (17 of many)	2020-02-26 14:26:36 +00:00
ntb_hw	ntb_hw_intel: fix xeon NTB gen3 bar disable logic	2021-10-04 06:53:26 -07:00
test	ntb_tool: ubuf is too small to hold a human readable 64 bit value	2020-10-21 17:11:57 +00:00
ntb.c	Mark more nodes as CTLFLAG_MPSAFE or CTLFLAG_NEEDGIANT (17 of many)	2020-02-26 14:26:36 +00:00
ntb.h	Make ntb(4) send bus_get_dma_tag() requests to parent buses passing real	2019-11-14 04:34:58 +00:00
ntb_if.m	Add driver for NTB in AMD SoC.	2019-07-02 05:25:18 +00:00
ntb_transport.c	ntb_transport(4): Mark callouts MP-safe.	2021-08-23 22:29:46 -04:00
ntb_transport.h	Report NTB link speed to console and interface.	2017-04-23 14:25:51 +00:00