David Bright 52e1406947 ntb_hw_intel: fix xeon NTB gen3 bar disable logic ... In NTB gen3 driver, it was supposed to disable NTB bar access by default, but due to incorrect register access method, the bar disable logic does not work as expected. Those registers should be modified through NTB bar0 rather than PCI configuration space. Besides, we'd better to protect ourselves from a bad buddy node so ingress disable logic should be implemented together. Submitted by: Austin Zhang (austin.zhang@dell.com) Sponsored by: Dell EMC (cherry picked from commit e3cf7ebc1d)		2021-10-04 06:53:26 -07:00
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ntb_hw_amd.c	ntb: clean up empty lines in .c and .h files	2020-09-01 22:03:55 +00:00
ntb_hw_amd.h	Add support for Hygon NTB PCI device in ntb_hw_amd driver.	2020-02-14 15:04:56 +00:00
ntb_hw_intel.c	ntb_hw_intel: fix xeon NTB gen3 bar disable logic	2021-10-04 06:53:26 -07:00
ntb_hw_intel.h	ntb: Add Intel Xeon Gen3 support	2020-10-23 14:16:52 +00:00
ntb_hw_plx.c	o Don't include headers from iommu.h, include them from the header	2020-07-29 22:08:54 +00:00