Ruslan Bukin 9be0058ea0 riscv vmm: virtual timer support. ... Add a virtual timer implementation based on SBI Time extension. This is needed for Eswin EIC7700 SoC which does not include the newer SSTC extension. Timer interrupt pending bit (STIP) could not be cleared in the guest system, so rework interrupts handling: add new "interrupts_pending" field. Use it for timer interrupt only for now, but later we can extend to store all pending interrupts (Timer, IPI and External). With this I'm able to boot FreeBSD (SMP) guest on HiFive Premier P550, which is the first real hardware with RISC-V 'H'-spec included. Differential Revision: https://reviews.freebsd.org/D48133		2025-01-02 16:02:39 +00:00
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allwinner	aw_gpio: support Allwinner D1 GPIO	2024-12-10 17:30:13 -04:00
conf	riscv: connect eswin to the build.	2024-12-17 17:42:09 +00:00
eswin	riscv: connect eswin to the build.	2024-12-17 17:42:09 +00:00
include	riscv vmm: add SSTC extension check.	2024-12-17 10:35:44 +00:00
riscv	riscv: Permit spurious faults in kernel mode	2024-12-10 15:07:28 +00:00
sifive	riscv: Add SiFive CCache driver.	2024-12-17 11:28:25 +00:00
starfive	Add StarFive JH7110's STG clocks	2024-12-16 15:27:23 -04:00
thead	riscv: T-HEAD PBMT support	2024-11-25 17:08:04 -04:00
vmm	riscv vmm: virtual timer support.	2025-01-02 16:02:39 +00:00