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e9fa399180
The T-HEAD custom PTE bits are defined in such a way that the default/normal memory type is non-zero value. This _unthoughtful_ choice means that, unlike the Svpbmt and non-Svpbmt cases, this field cannot be left bare in our bootstrap PTEs, or the hardware will fail to proceed far enough in boot (cache strangeness). On the other hand, we cannot unconditionally apply the PTE_THEAD_MA_NONE attributes, as this is not compatible with spec-compliant RISC-V hardware, and will result in a fatal exception. Therefore, in order to handle this errata, we are forced to perform a check of the CPU type at the first moment possible. Do so, and fix up the PTEs with the correct memory attribute bits in the T-HEAD case. Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D47458
114 lines
3.7 KiB
C
114 lines
3.7 KiB
C
/*-
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* Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _MACHINE_CPU_H_
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#define _MACHINE_CPU_H_
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#ifndef LOCORE
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#include <machine/atomic.h>
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#include <machine/cpufunc.h>
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#include <machine/frame.h>
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#endif
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#define TRAPF_PC(tfp) ((tfp)->tf_sepc)
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#define TRAPF_USERMODE(tfp) (((tfp)->tf_sstatus & SSTATUS_SPP) == 0)
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#define cpu_getstack(td) ((td)->td_frame->tf_sp)
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#define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp))
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#define cpu_spinwait() /* nothing */
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#define cpu_lock_delay() DELAY(1)
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/*
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* Core manufacturer IDs, as reported by the mvendorid CSR.
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*/
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#define MVENDORID_UNIMPL 0x0
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#define MVENDORID_SIFIVE 0x489
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#define MVENDORID_THEAD 0x5b7
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/*
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* Micro-architecture ID register, marchid.
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*
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* IDs for open-source implementations are allocated globally. Commercial IDs
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* will have the most-significant bit set.
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*/
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#define MARCHID_UNIMPL 0x0
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#define MARCHID_MSB (1ul << (XLEN - 1))
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#define MARCHID_OPENSOURCE(v) (v)
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#define MARCHID_COMMERCIAL(v) (MARCHID_MSB | (v))
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#define MARCHID_IS_OPENSOURCE(m) (((m) & MARCHID_MSB) == 0)
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/*
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* Open-source marchid values.
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*
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* https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
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*/
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#define MARCHID_UCB_ROCKET MARCHID_OPENSOURCE(1)
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#define MARCHID_UCB_BOOM MARCHID_OPENSOURCE(2)
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#define MARCHID_UCB_SPIKE MARCHID_OPENSOURCE(5)
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#define MARCHID_UCAM_RVBS MARCHID_OPENSOURCE(10)
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/* SiFive marchid values */
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#define MARCHID_SIFIVE_U7 MARCHID_COMMERCIAL(7)
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/*
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* MMU virtual-addressing modes. Support for each level implies the previous,
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* so Sv48-enabled systems MUST support Sv39, etc.
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*/
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#define MMU_SV39 0x1 /* 3-level paging */
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#define MMU_SV48 0x2 /* 4-level paging */
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#define MMU_SV57 0x4 /* 5-level paging */
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#ifdef _KERNEL
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#ifndef LOCORE
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extern char btext[];
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extern char etext[];
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void cpu_halt(void) __dead2;
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void cpu_reset(void) __dead2;
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void fork_trampoline(void);
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void identify_cpu(u_int cpu);
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void printcpuinfo(u_int cpu);
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static __inline uint64_t
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get_cyclecount(void)
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{
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return (rdcycle());
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}
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#endif /* !LOCORE */
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#endif /* _KERNEL */
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#endif /* !_MACHINE_CPU_H_ */
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